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公开(公告)号：US20170140698A1
公开(公告)日：2017-05-18
申请号：US15417092
申请日：2017-01-26
Applicant: Samsung Display Co., Ltd.
Inventor： Jung Hwan HWANG , Beom Jun KIM , Seong Yeol SYN , Bong-Jun LEE , You Mee HYUN
CPC classification number: G09G3/2092 , G09G3/3648 , G09G3/3677 , G09G2300/0809 , G09G2310/0286 , G11C19/28
Abstract: A display panel is provided. The display panel includes a display area comprising a gate line and a data line, and a gate driver connected to a terminal of the gate line. The gate driver includes a plurality of stages that are integrated on a substrate, and each stage comprises an inverter unit, an output unit, and a Q node stabilization unit. The output unit includes a first transistor and a first capacitor, wherein the first transistor includes an input terminal for receiving a clock signal, a control terminal connected to a node Q and an output terminal connected to a gate voltage output terminal to output a gate voltage. A Vgs voltage of a transistor in the Q node stabilization unit has a value of equal to or less than 0 V when the output unit outputs a gate-on voltage.
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公开(公告)号：US20210209997A1
公开(公告)日：2021-07-08
申请号：US17209068
申请日：2021-03-22
Applicant: Samsung Display Co., Ltd.
Inventor： Jung Hwan HWANG , Beom Jun KIM , Seong Yeol SYN , Bong-Jun LEE , You Mee HYUN
Abstract: A display panel is provided. The display panel includes a display area comprising a gate line and a data line, and a gate driver connected to a terminal of the gate line. The gate driver includes a plurality of stages that are integrated on a substrate, and each stage comprises an inverter unit, an output unit, and a Q node stabilization unit. The output unit includes a first transistor and a first capacitor, wherein the first transistor includes an input terminal for receiving a clock signal, a control terminal connected to a node Q, and an output terminal connected to a gate voltage output terminal to output a gate voltage. A Vgs voltage of a transistor in the Q node stabilization unit has a value of equal to or less than 0 V when the output unit outputs a gate-on voltage.
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公开(公告)号：US20230252932A1
公开(公告)日：2023-08-10
申请号：US18135212
申请日：2023-04-17
Applicant: Samsung Display Co., Ltd.
Inventor： Jung Hwan HWANG , Beom Jun KIM , Seong Yeol SYN , Bong-Jun LEE , You Mee HYUN
CPC classification number: G09G3/2092 , G09G3/3648 , G09G3/3677 , G11C19/28 , G09G2310/0286 , G09G2300/0809
Abstract: A display panel is provided. The display panel includes a display area comprising a gate line and a data line, and a gate driver connected to a terminal of the gate line. The gate driver includes a plurality of stages that are integrated on a substrate, and each stage comprises an inverter unit, an output unit, and a Q node stabilization unit. The output unit includes a first transistor and a first capacitor, wherein the first transistor includes an input terminal for receiving a clock signal, a control terminal connected to a node Q, and an output terminal connected to a gate voltage output terminal to output a gate voltage. A Vgs voltage of a transistor in the Q node stabilization unit has a value of equal to or less than 0 V when the output unit outputs a gate-on voltage.
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Patent Agency Ranking
公开(公告)号：US20200020269A1
公开(公告)日：2020-01-16
申请号：US16583018
申请日：2019-09-25
Applicant: Samsung Display Co., Ltd.
Inventor： Jung Hwan HWANG , Beom Jun KIM , Seong Yeol SYN , Bong-Jun LEE , You Mee HYUN
Abstract: A display panel is provided. The display panel includes a display area comprising a gate line and a data line, and a gate driver connected to a terminal of the gate line. The gate driver includes a plurality of stages that are integrated on a substrate, and each stage comprises an inverter unit, an output unit, and a Q node stabilization unit. The output unit includes a first transistor and a first capacitor, wherein the first transistor includes an input terminal for receiving a clock signal, a control terminal connected to a node Q, and an output terminal connected to a gate voltage output terminal to output a gate voltage. A Vgs voltage of a transistor in the Q node stabilization unit has a value of equal to or less than 0 V when the output unit outputs a gate-on voltage.
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公开(公告)号：US20220254310A1
公开(公告)日：2022-08-11
申请号：US17728584
申请日：2022-04-25
Applicant: SAMSUNG DISPLAY CO., LTD.
Inventor： Kang Nam KIM , You Mee HYUN , Beom Jun KIM , Jong Hwan LEE , Sung Hoon LIM , Duc Han CHO
IPC: G09G3/3266 , G09G3/20 , G11C19/28 , G09G3/36
Abstract: A gate driving circuit including a controller for providing a first carry signal to a control node, a first pull-up portion for outputting a first clock signal as a first gate signal in accordance with a signal provided to the control node, and a second pull-up portion for outputting a second clock signal with a phase that is different from the first clock signal as a second gate signal in accordance with the signal provided to the control node.
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公开(公告)号：US20210384283A1
公开(公告)日：2021-12-09
申请号：US17338461
申请日：2021-06-03
Applicant: Samsung Display Co., Ltd.
Inventor： Hyung Gi JUNG , Ki Hwan KIM , Beom Jin KIM , Soon Chang YEON , Sung Hyun LEE , Jae Min LEE , Jae Young LEE , You Mee HYUN
Abstract: A display device includes: a first base on which a display area and a non-display area are defined; a light-emitting element on the first base and in the display area; a second base facing the first base and above the light-emitting element; a color filter on a surface of the second base that faces the first base and overlapping the light-emitting element; a wavelength conversion pattern on the color filter; a sealing member in the non-display area between the first base and the second base; and a sink pattern in the non-display area, wherein the sink pattern is between the sealing member and the display area when viewed from a plan view.
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公开(公告)号：US20160171950A1
公开(公告)日：2016-06-16
申请号：US14742915
申请日：2015-06-18
Applicant: Samsung Display Co., Ltd.
Inventor： Duc-Han CHO , Kang Nam KIM , Beom Jun KIM , You Mee HYUN
IPC: G09G3/36
CPC classification number: G09G3/3677 , G09G3/3648 , G09G2310/0283 , G09G2310/0286 , G09G2310/08 , G09G2330/021 , G11C19/287
Abstract: A display device includes: a plurality of pixels; a plurality of gate lines connected to the plurality of pixels; an output terminal connected to a gate line of the gate lines; a first transistor connected to a first node, a first clock signal input terminal and the output terminal; a second transistor connected to a second clock signal input terminal, a low-level power voltage and the output terminal; a third transistor connected to a second node, the low-level power voltage and the first node; a fourth transistor connected to a first forward input terminal, the low-level power voltage and the second node; and a fifth transistor connected to a first backward input terminal, the low-level power voltage and the second node.
Abstract translation: 显示装置包括：多个像素; 连接到所述多个像素的多个栅极线; 连接到栅极线的栅极线的输出端子; 连接到第一节点的第一晶体管，第一时钟信号输入端和输出端; 连接到第二时钟信号输入端子的第二晶体管，低电平电源电压和输出端子; 连接到第二节点的第三晶体管，低电平电源电压和第一节点; 连接到第一正向输入端子的第四晶体管，低电平电源电压和第二节点; 以及与第一反向输入端子，低电平电源电压和第二节点连接的第五晶体管。
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公开(公告)号：US20140267214A1
公开(公告)日：2014-09-18
申请号：US14203272
申请日：2014-03-10
Applicant: Samsung Display Co., Ltd.
Inventor： Jung Hwan HWANG , Beom Jun KIM , Seong Yeol SYN , Bong-Jun LEE , You Mee HYUN
IPC: G09G3/36
CPC classification number: G09G3/2092 , G09G3/3648 , G09G3/3677 , G09G2300/0809 , G09G2310/0286 , G11C19/28
Abstract: A display panel is provided. The display panel includes a display area comprising a gate line and a data line, and a gate driver connected to a terminal of the gate line. The gate driver includes a plurality of stages that are integrated on a substrate, and each stage comprises an inverter unit, an output unit, and a Q node stabilization unit. The output unit includes a first transistor and a first capacitor, wherein the first transistor includes an input terminal for receiving a clock signal, a control terminal connected to a node Q, and an output terminal connected to a gate voltage output terminal to output a gate voltage. A Vgs voltage of a transistor in the Q node stabilization unit has a value of equal to or less than 0 V when the output unit outputs a gate-on voltage.
Abstract translation: 提供显示面板。 显示面板包括包括栅线和数据线的显示区域，以及连接到栅极线的端子的栅极驱动器。 栅极驱动器包括集成在衬底上的多个级，并且每个级包括逆变器单元，输出单元和Q结点稳定单元。 输出单元包括第一晶体管和第一电容器，其中第一晶体管包括用于接收时钟信号的输入端子，连接到节点Q的控制端子和连接到栅极电压输出端子的输出端子以输出栅极 电压。 当输出单元输出栅极导通电压时，Q节点稳定单元中的晶体管的Vgs电压具有等于或小于0V的值。
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