公开(公告)号：US20210209997A1

公开(公告)日：2021-07-08

申请号：US17209068

申请日：2021-03-22

Applicant: Samsung Display Co., Ltd.

Inventor： Jung Hwan HWANG ,  Beom Jun KIM ,  Seong Yeol SYN ,  Bong-Jun LEE ,  You Mee HYUN

IPC: G09G3/20 ,  G09G3/36 ,  G11C19/28

Abstract: A display panel is provided. The display panel includes a display area comprising a gate line and a data line, and a gate driver connected to a terminal of the gate line. The gate driver includes a plurality of stages that are integrated on a substrate, and each stage comprises an inverter unit, an output unit, and a Q node stabilization unit. The output unit includes a first transistor and a first capacitor, wherein the first transistor includes an input terminal for receiving a clock signal, a control terminal connected to a node Q, and an output terminal connected to a gate voltage output terminal to output a gate voltage. A Vgs voltage of a transistor in the Q node stabilization unit has a value of equal to or less than 0 V when the output unit outputs a gate-on voltage.

公开(公告)号：US20160351158A1

公开(公告)日：2016-12-01

申请号：US15231246

申请日：2016-08-08

Applicant: Samsung Display Co., Ltd.

Inventor： Beom-Jun KIM ,  Myung-Koo HUR ,  Bong-Jun LEE ,  Yeon-Kyu MOON ,  Myung-Sub LEE ,  Gyu-Tae KIM

IPC: G09G3/36

CPC classification number: G09G3/3688 ,  G09G3/36 ,  G09G3/3677 ,  G09G2300/0426 ,  G09G2310/0251 ,  G09G2310/0291 ,  G09G2310/08 ,  G11C19/28 ,  H03K17/693

Abstract: A gate driving circuit including a plurality of stages connected with each other and configured to output a plurality of gate signals. An n-th (n is a natural number) stage including a gate output part including a first transistor connected between a clock signal and an output node outputting an n-th gate signal, the first transistor having a gate electrode connected to a control node, a carry part connected between the clock signal and a carry node outputting an n-th carry signal, a first node control part connected between the output node and a first low voltage, and a second node control part including at least one transistor connected between the control node and a second low voltage different from the first low voltage.

Abstract translation: 一种栅极驱动电路，包括彼此连接的多个级并且被配置为输出多个栅极信号。 第n（n是自然数）级，包括栅极输出部分，该栅极输出部分包括连接在时钟信号和输出第n个栅极信号的输出节点之间的第一晶体管，第一晶体管具有连接到控制节点 连接在时钟信号和输出第n个进位信号的进位节点之间的进位部分，连接在输出节点和第一低电压之间的第一节点控制部分和包括至少一个晶体管的第二节点控制部分， 控制节点和与第一低电压不同的第二低电压。

公开(公告)号：US20150268525A1

公开(公告)日：2015-09-24

申请号：US14476570

申请日：2014-09-03

Applicant: Samsung Display Co., Ltd.

Inventor： Yun HEO ,  Bong-Jun LEE ,  Dong Wuuk SEO ,  Jong Woong CHANG

IPC: G02F1/1362 ,  G02F1/1335 ,  G02F1/1343 ,  G02F1/1368 ,  G02F1/1339

CPC classification number: G02F1/136227 ,  G02F1/133707 ,  G02F2201/40

Abstract: A liquid crystal display includes: a first substrate; a gate line and a common voltage line that are on the first substrate; a gate insulating layer on the gate line and the common voltage line; a semiconductor layer on the gate insulating layer; a data line and a drain electrode that are on the semiconductor layer; a pixel electrode on the data line and the drain electrode; a passivation layer on the pixel electrode; a common electrode on the passivation layer; a second substrate; and a liquid crystal layer interposed between the first and second substrates. The pixel electrode contacts the drain electrode via a first contact hole, the common electrode contacts the common voltage line via a second contact hole in the gate insulating layer and the passivation layer, and the first and second contact holes are adjacently disposed in a thin film transistor forming region.

Abstract translation: 液晶显示器包括：第一基板; 位于第一基板上的栅极线和公共电压线; 栅极线和公共电压线上的栅极绝缘层; 栅极绝缘层上的半导体层; 数据线和漏电极，位于半导体层上; 数据线和漏电极上的像素电极; 像素电极上的钝化层; 钝化层上的公共电极; 第二基板; 以及插入在第一和第二基板之间的液晶层。 像素电极经由第一接触孔接触漏极，公共电极经由栅极绝缘层和钝化层中的第二接触孔接触公共电压线，并且第一和第二接触孔相邻地设置在薄膜 晶体管形成区域。

公开(公告)号：US20140267214A1

公开(公告)日：2014-09-18

申请号：US14203272

申请日：2014-03-10

Applicant: Samsung Display Co., Ltd.

Inventor： Jung Hwan HWANG ,  Beom Jun KIM ,  Seong Yeol SYN ,  Bong-Jun LEE ,  You Mee HYUN

IPC: G09G3/36

CPC classification number: G09G3/2092 ,  G09G3/3648 ,  G09G3/3677 ,  G09G2300/0809 ,  G09G2310/0286 ,  G11C19/28

Abstract: A display panel is provided. The display panel includes a display area comprising a gate line and a data line, and a gate driver connected to a terminal of the gate line. The gate driver includes a plurality of stages that are integrated on a substrate, and each stage comprises an inverter unit, an output unit, and a Q node stabilization unit. The output unit includes a first transistor and a first capacitor, wherein the first transistor includes an input terminal for receiving a clock signal, a control terminal connected to a node Q, and an output terminal connected to a gate voltage output terminal to output a gate voltage. A Vgs voltage of a transistor in the Q node stabilization unit has a value of equal to or less than 0 V when the output unit outputs a gate-on voltage.

Abstract translation: 提供显示面板。 显示面板包括包括栅线和数据线的显示区域，以及连接到栅极线的端子的栅极驱动器。 栅极驱动器包括集成在衬底上的多个级，并且每个级包括逆变器单元，输出单元和Q结点稳定单元。 输出单元包括第一晶体管和第一电容器，其中第一晶体管包括用于接收时钟信号的输入端子，连接到节点Q的控制端子和连接到栅极电压输出端子的输出端子以输出栅极 电压。 当输出单元输出栅极导通电压时，Q节点稳定单元中的晶体管的Vgs电压具有等于或小于0V的值。

公开(公告)号：US20230252932A1

公开(公告)日：2023-08-10

申请号：US18135212

申请日：2023-04-17

Applicant: Samsung Display Co., Ltd.

Inventor： Jung Hwan HWANG ,  Beom Jun KIM ,  Seong Yeol SYN ,  Bong-Jun LEE ,  You Mee HYUN

IPC: G09G3/20 ,  G09G3/36 ,  G11C19/28

CPC classification number: G09G3/2092 ,  G09G3/3648 ,  G09G3/3677 ,  G11C19/28 ,  G09G2310/0286 ,  G09G2300/0809

Abstract: A display panel is provided. The display panel includes a display area comprising a gate line and a data line, and a gate driver connected to a terminal of the gate line. The gate driver includes a plurality of stages that are integrated on a substrate, and each stage comprises an inverter unit, an output unit, and a Q node stabilization unit. The output unit includes a first transistor and a first capacitor, wherein the first transistor includes an input terminal for receiving a clock signal, a control terminal connected to a node Q, and an output terminal connected to a gate voltage output terminal to output a gate voltage. A Vgs voltage of a transistor in the Q node stabilization unit has a value of equal to or less than 0 V when the output unit outputs a gate-on voltage.

公开(公告)号：US20200020269A1

公开(公告)日：2020-01-16

申请号：US16583018

申请日：2019-09-25

Applicant: Samsung Display Co., Ltd.

Inventor： Jung Hwan HWANG ,  Beom Jun KIM ,  Seong Yeol SYN ,  Bong-Jun LEE ,  You Mee HYUN

IPC: G09G3/20 ,  G11C19/28 ,  G09G3/36

Abstract: A display panel is provided. The display panel includes a display area comprising a gate line and a data line, and a gate driver connected to a terminal of the gate line. The gate driver includes a plurality of stages that are integrated on a substrate, and each stage comprises an inverter unit, an output unit, and a Q node stabilization unit. The output unit includes a first transistor and a first capacitor, wherein the first transistor includes an input terminal for receiving a clock signal, a control terminal connected to a node Q, and an output terminal connected to a gate voltage output terminal to output a gate voltage. A Vgs voltage of a transistor in the Q node stabilization unit has a value of equal to or less than 0 V when the output unit outputs a gate-on voltage.

公开(公告)号：US20150194116A1

公开(公告)日：2015-07-09

申请号：US14319233

申请日：2014-06-30

Applicant: SAMSUNG DISPLAY CO., LTD.

Inventor： Bong-Jun LEE ,  Ji-Young JEONG ,  Ju-Hyeon BAEK ,  Dong-Wuuk SEO ,  Byeong-Jae AHN

IPC: G09G3/36 ,  G02F1/1335 ,  G02F1/1362

CPC classification number: G09G3/3685 ,  G02F1/133512 ,  G02F1/133514 ,  G02F2001/133388 ,  G09G2310/0283 ,  Y10T29/49117

Abstract: A display panel includes a plurality of pixels disposed in an active area and arranged substantially in a matrix form including a pixel row and a pixel column, a first gate line disposed adjacent to a first side n of the pixel row and connected to a first pixel in the pixel row, a second gate line disposed adjacent to a second side of the pixel row and connected to a second pixel in the pixel row, a plurality of data lines crossing the first and second gate lines, where the pixels in a pair of adjacent pixel columns are connected to a same data line, and a blocking pattern which overlaps a pixel column disposed in an end portion of the active area.

Abstract translation: 显示面板包括设置在有效区域中并且基本上以矩阵形式布置的多个像素，其包括像素行和像素列，第一栅极线与像素行的第一侧n相邻并且连接到第一像素 在所述像素行中，与所述像素行的第二侧相邻并且连接到所述像素行中的第二像素的第二栅极线，与所述第一和第二栅极线交叉的多条数据线， 相邻像素列连接到相同的数据线，以及与设置在有源区的端部中的像素列重叠的阻挡图案。

公开(公告)号：US20170140698A1

公开(公告)日：2017-05-18

申请号：US15417092

申请日：2017-01-26

Applicant: Samsung Display Co., Ltd.

Inventor： Jung Hwan HWANG ,  Beom Jun KIM ,  Seong Yeol SYN ,  Bong-Jun LEE ,  You Mee HYUN

IPC: G09G3/20 ,  G11C19/28

CPC classification number: G09G3/2092 ,  G09G3/3648 ,  G09G3/3677 ,  G09G2300/0809 ,  G09G2310/0286 ,  G11C19/28

Abstract: A display panel is provided. The display panel includes a display area comprising a gate line and a data line, and a gate driver connected to a terminal of the gate line. The gate driver includes a plurality of stages that are integrated on a substrate, and each stage comprises an inverter unit, an output unit, and a Q node stabilization unit. The output unit includes a first transistor and a first capacitor, wherein the first transistor includes an input terminal for receiving a clock signal, a control terminal connected to a node Q and an output terminal connected to a gate voltage output terminal to output a gate voltage. A Vgs voltage of a transistor in the Q node stabilization unit has a value of equal to or less than 0 V when the output unit outputs a gate-on voltage.

公开(公告)号：US20150195924A1

公开(公告)日：2015-07-09

申请号：US14312857

申请日：2014-06-24

Applicant: Samsung Display Co., Ltd.

Inventor： Byeong-Jae AHN ,  Ju-Hyeon BAEK ,  Dong-Wuuk SEO ,  Bong-Jun LEE

IPC: H05K5/00 ,  H05K5/02

CPC classification number: H05K5/02 ,  G02F1/133308 ,  G02F2001/13332 ,  G02F2001/133328 ,  G02F2201/46

Abstract: A display panel includes a first substrate, a second substrate which faces the first substrate, is smaller than the first substrate so that an edge of the first substrate is exposed in a plan view, a fixing member disposed on the exposed edge of the first substrate, and a bonding member disposed between the first substrate and the fixing member.

Abstract translation: 显示面板包括第一基板，面对第一基板的第二基板，比第一基板小，使得第一基板的边缘在平面图中露出，固定部件设置在第一基板的露出边缘上 以及设置在第一基板和固定部件之间的接合部件。

公开(公告)号：US20140226100A1

公开(公告)日：2014-08-14

申请号：US14139188

申请日：2013-12-23

Applicant: Samsung Display Co., Ltd.

Inventor： Duk-Sung KIM ,  Bong-Jun LEE ,  Sung Man KIM ,  Seul Ki KIM ,  Jin Yun KIM ,  Dong Wuuk SEO ,  Min Hee SON

IPC: G02F1/133 ,  G02F1/1343

CPC classification number: G02F1/134309 ,  G02F1/13306 ,  G02F1/133345 ,  G02F1/1343 ,  G02F1/134363 ,  G02F1/13439 ,  G02F1/136286 ,  G02F1/1368 ,  G02F2001/134318 ,  G02F2001/134372 ,  G02F2001/136272 ,  G02F2201/121 ,  H01L27/1225 ,  H01L27/124 ,  H01L29/7869

Abstract: A display, includes: a substrate; first signal lines (FSLs) disposed on the substrate and extending in substantially a first direction; a gate insulating layer (GIL) disposed on the FSLs; a first electrode disposed on the GIL; a thin film transistor (TFT) connected to a FSL of the FSLs and including the GIL and the first electrode; a pixel electrode (PE) extending in substantially the first direction, connected to the TFT, and configured to receive a data voltage from the TFT; a common electrode (CE) overlapping with at least a portion of the PE; and a first insulating layer disposed between the PE and CE. One of the PE and the CE has a planar shape and the other includes branch electrodes overlapping with the planar shape and extending substantially parallel to the FSL. At least a portion of the CE overlaps with at least a portion of the FSL.

Abstract translation: 一种显示器，包括：基板; 第一信号线（FSL），其设置在基板上并且基本上沿第一方向延伸; 设置在FSL上的栅极绝缘层（GIL）; 设置在GIL上的第一电极; 连接到FSL的FSL并且包括GIL和第一电极的薄膜晶体管（TFT）; 基本上沿第一方向延伸的像素电极（PE），连接到TFT，并被配置为从TFT接收数据电压; 与PE的至少一部分重叠的公共电极（CE）; 以及设置在PE和CE之间的第一绝缘层。 PE和CE中的一个具有平面形状，另一个包括与平面形状重叠并且基本上平行于FSL延伸的分支电极。 CE的至少一部分与FSL的至少一部分重叠。