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公开(公告)号：US20240331608A1
公开(公告)日：2024-10-03
申请号：US18732585
申请日：2024-06-03
发明人： Kang Nam KIM , Sung Hoon LIM , Woo Geun LEE , Kyu Sik CHO , Jae Beom CHOI
IPC分类号： G09G3/20 , G09G3/3233 , G09G3/3266
CPC分类号： G09G3/2092 , G09G3/3233 , G09G3/3266 , G09G2310/0202 , G09G2310/0267 , G09G2310/0275 , G09G2310/0286 , G09G2310/08
摘要： A scan driver includes a plurality of stages. An nth (n is a natural number) stage among the stages includes: a first and a second input circuit for controlling a voltage of a first node in response to a carry signal of a previous stage and a next stage, respectively; a first output circuit for outputting an nth carry signal corresponding to a carry clock signal in response to the voltage of the first node; a second output circuit for outputting an nth scan and an nth sensing signal corresponding to a scan and a sensing clock signal, respectively, in response to the voltage of the first node; and a sampling circuit for storing the carry signal of the previous stage in response to a first select signal, and for supplying a control voltage to the first node in response to a second select signal and the stored carry signal.
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公开(公告)号：US20230245612A1
公开(公告)日：2023-08-03
申请号：US18132704
申请日：2023-04-10
发明人： Kang Nam KIM , Sung Hoon LIM , Woo Geun LEE , Kyu Sik CHO , Jae Beom CHOI
IPC分类号： G09G3/20
CPC分类号： G09G3/2092 , G09G3/3266 , G09G2310/08 , G09G2310/0267 , G09G2310/0275
摘要： A scan driver includes a plurality of stages. An nth (n is a natural number) stage among the stages includes: a first and a second input circuit for controlling a voltage of a first node in response to a carry signal of a previous stage and a next stage, respectively; a first output circuit for outputting an nth carry signal corresponding to a carry clock signal in response to the voltage of the first node; a second output circuit for outputting an nth scan and an nth sensing signal corresponding to a scan and a sensing clock signal, respectively, in response to the voltage of the first node; and a sampling circuit for storing the carry signal of the previous stage in response to a first select signal, and for supplying a control voltage to the first node in response to a second select signal and the stored carry signal.
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公开(公告)号：US20220254310A1
公开(公告)日：2022-08-11
申请号：US17728584
申请日：2022-04-25
发明人： Kang Nam KIM , You Mee HYUN , Beom Jun KIM , Jong Hwan LEE , Sung Hoon LIM , Duc Han CHO
IPC分类号： G09G3/3266 , G09G3/20 , G11C19/28 , G09G3/36
摘要： A gate driving circuit including a controller for providing a first carry signal to a control node, a first pull-up portion for outputting a first clock signal as a first gate signal in accordance with a signal provided to the control node, and a second pull-up portion for outputting a second clock signal with a phase that is different from the first clock signal as a second gate signal in accordance with the signal provided to the control node.
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公开(公告)号：US20220005402A1
公开(公告)日：2022-01-06
申请号：US17478825
申请日：2021-09-17
发明人： Kang Nam KIM , Sung Hoon LIM , Woo Geun LEE , Kyu Sik CHO , Jae Beom CHOI
IPC分类号： G09G3/20
摘要： A scan driver includes a plurality of stages. An nth (n is a natural number) stage among the stages includes: a first and a second input circuit for controlling a voltage of a first node in response to a carry signal of a previous stage and a next stage, respectively; a first output circuit for outputting an nth carry signal corresponding to a carry clock signal in response to the voltage of the first node; a second output circuit for outputting an nth scan and an nth sensing signal corresponding to a scan and a sensing clock signal, respectively, in response to the voltage of the first node; and a sampling circuit for storing the carry signal of the previous stage in response to a first select signal, and for supplying a control voltage to the first node in response to a second select signal and the stored carry signal.
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公开(公告)号：US20200372851A1
公开(公告)日：2020-11-26
申请号：US16875682
申请日：2020-05-15
发明人： Kang Nam KIM , Sung Hoon LIM , Woo Geun LEE , Kyu Sik CHO , Jae Beom CHOI
IPC分类号： G09G3/20
摘要： A scan driver includes a plurality of stages. An nth (n is a natural number) stage among the stages includes: a first and a second input circuit for controlling a voltage of a first node in response to a carry signal of a previous stage and a next stage, respectively; a first output circuit for outputting an nth carry signal corresponding to a carry clock signal in response to the voltage of the first node; a second output circuit for outputting an nth scan and an nth sensing signal corresponding to a scan and a sensing clock signal, respectively, in response to the voltage of the first node; and a sampling circuit for storing the carry signal of the previous stage in response to a first select signal, and for supplying a control voltage to the first node in response to a second select signal and the stored carry signal.
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公开(公告)号：US20160171950A1
公开(公告)日：2016-06-16
申请号：US14742915
申请日：2015-06-18
发明人： Duc-Han CHO , Kang Nam KIM , Beom Jun KIM , You Mee HYUN
IPC分类号： G09G3/36
CPC分类号： G09G3/3677 , G09G3/3648 , G09G2310/0283 , G09G2310/0286 , G09G2310/08 , G09G2330/021 , G11C19/287
摘要： A display device includes: a plurality of pixels; a plurality of gate lines connected to the plurality of pixels; an output terminal connected to a gate line of the gate lines; a first transistor connected to a first node, a first clock signal input terminal and the output terminal; a second transistor connected to a second clock signal input terminal, a low-level power voltage and the output terminal; a third transistor connected to a second node, the low-level power voltage and the first node; a fourth transistor connected to a first forward input terminal, the low-level power voltage and the second node; and a fifth transistor connected to a first backward input terminal, the low-level power voltage and the second node.
摘要翻译： 显示装置包括：多个像素; 连接到所述多个像素的多个栅极线; 连接到栅极线的栅极线的输出端子; 连接到第一节点的第一晶体管，第一时钟信号输入端和输出端; 连接到第二时钟信号输入端子的第二晶体管，低电平电源电压和输出端子; 连接到第二节点的第三晶体管，低电平电源电压和第一节点; 连接到第一正向输入端子的第四晶体管，低电平电源电压和第二节点; 以及与第一反向输入端子，低电平电源电压和第二节点连接的第五晶体管。
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