公开(公告)号：US09673195B2

公开(公告)日：2017-06-06

申请号：US14264694

申请日：2014-04-29

Applicant: Samsung Electronics Co., LTD.

Inventor： Man-Hyoung Ryoo ,  Gi-Sung Yeo ,  Si-Hyeung Lee ,  Gyu-Chul Kim ,  Sung-Gon Jung ,  Chang-Min Park ,  Hoo-Sung Cho

IPC: H01L27/11 ,  H01L27/088 ,  G11C11/412 ,  H01L27/02

CPC classification number: H01L27/088 ,  G11C11/412 ,  H01L27/0203 ,  H01L27/1104 ,  Y10S257/903

Abstract: According to some embodiments of the invention, a substrate doped with a P type impurity is provided. An N type impurity is doped into the substrate to divide the substrate into a P type impurity region and an N type impurity region. Active patterns having a first pitch are formed in the P type and N type impurity regions. Gate patterns having a second pitch are formed on the active patterns in a direction substantially perpendicular to the active patterns. Other embodiments are described and claimed.