公开(公告)号：US20180211968A1

公开(公告)日：2018-07-26

申请号：US15923408

申请日：2018-03-16

Applicant: Samsung Electronics Co., Ltd.

Inventor： Seung-Min Lee ,  Hoo-Sung Cho ,  Jeong-Seok Nam ,  Jong-Min Lee ,  Yong-Joon Choi

IPC: H01L27/11565 ,  H01L27/11582 ,  H01L21/768 ,  H01L23/528 ,  H01L27/11575 ,  H01L27/11573 ,  H01L23/544 ,  H01L27/1157 ,  H01L23/522

CPC classification number: H01L27/11565 ,  H01L21/76816 ,  H01L21/76877 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/544 ,  H01L27/1157 ,  H01L27/11573 ,  H01L27/11575 ,  H01L27/11582 ,  H01L2223/5442 ,  H01L2223/54433 ,  H01L2223/54453

Abstract: A vertical memory device includes a substrate, a plurality of channels on the substrate and extending in a first direction that is vertical to a top surface of the substrate, a plurality of gate lines stacked on top of each other on the substrate, a plurality of wiring over the gate lines and electrically connected to the gate lines, and an identification pattern on the substrate at the same level as a level of at least one of the wirings. The gate lines surround the channels. The gate lines are spaced apart from each other along the first direction.

公开(公告)号：USRE48482E1

公开(公告)日：2021-03-23

申请号：US16804630

申请日：2020-02-28

Applicant: Samsung Electronics Co., Ltd.

Inventor： Seung-Min Lee ,  Hoo-Sung Cho ,  Jeong-Seok Nam ,  Jong-Min Lee ,  Yong-Joon Choi

IPC: H01L27/11565 ,  H01L27/11582 ,  H01L21/768 ,  H01L27/1157 ,  H01L23/528 ,  H01L23/522 ,  H01L27/11575 ,  H01L27/11573 ,  H01L23/544

Abstract: A vertical memory device includes a substrate, a plurality of channels on the substrate and extending in a first direction that is vertical to a top surface of the substrate, a plurality of gate lines stacked on top of each other on the substrate, a plurality of wiring over the gate lines and electrically connected to the gate lines, and an identification pattern on the substrate at the same level as a level of at least one of the rings. The gate lines surround the channels. The gate lines are spaced apart from each other along the first direction.

公开(公告)号：US09165611B2

公开(公告)日：2015-10-20

申请号：US14157830

申请日：2014-01-17

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jang-Gn Yun ,  Hong-Soo Kim ,  Hoo-Sung Cho

IPC: H01L23/48 ,  G11C5/06 ,  H01L27/105 ,  H01L27/115 ,  H01L27/06

CPC classification number: G11C5/063 ,  H01L27/0688 ,  H01L27/1052 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11548 ,  H01L27/11556 ,  H01L27/11575 ,  H01L27/11582

Abstract: Wiring structures of three-dimensional semiconductor devices and methods of forming the same are provided. The wiring structures may include an upper wordline and a lower wordline, each of which extends in a longitudinal direction. The upper wordline may include a recessed portion that extends for only a portion of the upper wordline in a transverse direction and the lower wordline may include a wiring area exposed by the recessed portion of the upper wordline. The wiring structures may also include an upper contact plug contacting the upper wordline and a lower contact plug contacting the wiring area. The upper and lower contact plugs may extend in a vertical direction.

Abstract translation: 提供三维半导体器件的接线结构及其形成方法。 布线结构可以包括上字线和下字线，每个字线在纵向方向上延伸。 上字线可以包括在横向方向上仅延伸上部字线的一部分的凹部，下部字线可以包括由上部字线的凹部露出的布线区域。 布线结构还可以包括接触上部字线的上部接触插塞和与接线区域接触的下部接触插头。 上下接触塞可以在垂直方向上延伸。

公开(公告)号：US10304847B2

公开(公告)日：2019-05-28

申请号：US15923408

申请日：2018-03-16

Applicant: Samsung Electronics Co., Ltd.

Inventor： Seung-Min Lee ,  Hoo-Sung Cho ,  Jeong-Seok Nam ,  Jong-Min Lee ,  Yong-Joon Choi

IPC: H01L27/11565 ,  H01L27/11582 ,  H01L23/544 ,  H01L27/11573 ,  H01L27/11575 ,  H01L23/522 ,  H01L23/528 ,  H01L27/1157 ,  H01L21/768

Abstract: A vertical memory device includes a substrate, a plurality of channels on the substrate and extending in a first direction that is vertical to a top surface of the substrate, a plurality of gate lines stacked on top of each other on the substrate, a plurality of wiring over the gate lines and electrically connected to the gate lines, and an identification pattern on the substrate at the same level as a level of at least one of the wirings. The gate lines surround the channels. The gate lines are spaced apart from each other along the first direction.

公开(公告)号：US09673195B2

公开(公告)日：2017-06-06

申请号：US14264694

申请日：2014-04-29

Applicant: Samsung Electronics Co., LTD.

Inventor： Man-Hyoung Ryoo ,  Gi-Sung Yeo ,  Si-Hyeung Lee ,  Gyu-Chul Kim ,  Sung-Gon Jung ,  Chang-Min Park ,  Hoo-Sung Cho

IPC: H01L27/11 ,  H01L27/088 ,  G11C11/412 ,  H01L27/02

CPC classification number: H01L27/088 ,  G11C11/412 ,  H01L27/0203 ,  H01L27/1104 ,  Y10S257/903

Abstract: According to some embodiments of the invention, a substrate doped with a P type impurity is provided. An N type impurity is doped into the substrate to divide the substrate into a P type impurity region and an N type impurity region. Active patterns having a first pitch are formed in the P type and N type impurity regions. Gate patterns having a second pitch are formed on the active patterns in a direction substantially perpendicular to the active patterns. Other embodiments are described and claimed.