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公开(公告)号：US11581026B2
公开(公告)日：2023-02-14
申请号：US17495862
申请日：2021-10-07
Applicant: Samsung Electronics Co., Ltd.
Inventor： Jaemin Choi , Daehyun Kwon , Buyeon Lee
Abstract: A data receiving device of a memory device comprises a first pre-amplifier configured to receive previous data, a first reference voltage, and input data, and to output differential signals by comparing the input data with the first reference voltage in response to a clock, when the first pre-amplifier is selected in response to the previous data, a second pre-amplifier configured to receive inverted previous data, a second reference voltage, different from the first reference voltage, and the input data, and outputting a common signal in response to the clock, when the second pre-amplifier is unselected in response to the previous data; and an amplifier configured to receive the differential signals and the common signal, and to latch the input data by amplifying the differential signals.
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Patent Agency Ranking
公开(公告)号：US20210174844A1
公开(公告)日：2021-06-10
申请号：US16930561
申请日：2020-07-16
Applicant: Samsung Electronics Co., Ltd.
Inventor： Jaemin Choi , Daehyun Kwon , Buyeon Lee
Abstract: A data receiving device of a memory device comprises a first pre-amplifier configured to receive previous data, a first reference voltage, and input data, and to output differential signals by comparing the input data with the first reference voltage in response to a clock, when the first pre-amplifier is selected in response to the previous data, a second pre-amplifier configured to receive inverted previous data, a second reference voltage, different from the first reference voltage, and the input data, and outputting a common signal in response to the clock, when the second pre-amplifier is unselected in response to the previous data; and an amplifier configured to receive the differential signals and the common signal, and to latch the input data by amplifying the differential signals.
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公开(公告)号：US20210020227A1
公开(公告)日：2021-01-21
申请号：US16848418
申请日：2020-04-14
Applicant: Samsung Electronics Co., Ltd.
Inventor： Buyeon Lee , Taegyeong Kim , Taesung Kim , Byongmo Moon
IPC: G11C11/4093 , H03K19/00 , G06F3/06
Abstract: A memory device includes a pad region having a flag pad separated from an external host, and a signal pad connected to the external host. A bank region is provided having a plurality of memory cells therein. An on-die-termination (ODT) setting circuit is provided, which is configured to receive a control command including first data corresponding to termination resistance requested by the host, and a ODT enable signal. The setting circuit is configured to generate second data corresponding to the ODT resistance. An ODT enable circuit is provided, which is configured to output an ODT flag signal to the flag pad, in response to the control command and the ODT enable signal. A resistor circuit is provided, which is configured to connect the ODT resistance to the signal pad using the second data.
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公开(公告)号：US11238921B2
公开(公告)日：2022-02-01
申请号：US16848418
申请日：2020-04-14
Applicant: Samsung Electronics Co., Ltd.
Inventor： Buyeon Lee , Taegyeong Kim , Taesung Kim , Byongmo Moon
IPC: G11C11/4093 , G06F3/06 , H03K19/00
Abstract: A memory device includes a pad region having a flag pad separated from an external host, and a signal pad connected to the external host. A bank region is provided having a plurality of memory cells therein. An on-die-termination (ODT) setting circuit is provided, which is configured to receive a control command including first data corresponding to termination resistance requested by the host, and a ODT enable signal. The setting circuit is configured to generate second data corresponding to the ODT resistance. An ODT enable circuit is provided, which is configured to output an ODT flag signal to the flag pad, in response to the control command and the ODT enable signal. A resistor circuit is provided, which is configured to connect the ODT resistance to the signal pad using the second data.
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公开(公告)号：US20220028434A1
公开(公告)日：2022-01-27
申请号：US17495862
申请日：2021-10-07
Applicant: Samsung Electronics Co., Ltd.
Inventor： Jaemin Choi , Daehyun Kwon , Buyeon Lee
Abstract: A data receiving device of a memory device comprises a first pre-amplifier configured to receive previous data, a first reference voltage, and input data, and to output differential signals by comparing the input data with the first reference voltage in response to a clock, when the first pre-amplifier is selected in response to the previous data, a second pre-amplifier configured to receive inverted previous data, a second reference voltage, different from the first reference voltage, and the input data, and outputting a common signal in response to the clock, when the second pre-amplifier is unselected in response to the previous data; and an amplifier configured to receive the differential signals and the common signal, and to latch the input data by amplifying the differential signals.
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公开(公告)号：US11170825B2
公开(公告)日：2021-11-09
申请号：US16930561
申请日：2020-07-16
Applicant: Samsung Electronics Co., Ltd.
Inventor： Jaemin Choi , Daehyun Kwon , Buyeon Lee
Abstract: A data receiving device of a memory device comprises a first pre-amplifier configured to receive previous data, a first reference voltage, and input data, and to output differential signals by comparing the input data with the first reference voltage in response to a clock, when the first pre-amplifier is selected in response to the previous data, a second pre-amplifier configured to receive inverted previous data, a second reference voltage, different from the first reference voltage, and the input data, and outputting a common signal in response to the clock, when the second pre-amplifier is unselected in response to the previous data; and an amplifier configured to receive the differential signals and the common signal, and to latch the input data by amplifying the differential signals.
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