公开(公告)号：US11581026B2

公开(公告)日：2023-02-14

申请号：US17495862

申请日：2021-10-07

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jaemin Choi ,  Daehyun Kwon ,  Buyeon Lee

IPC: G11C7/02 ,  G11C7/06 ,  G11C7/10 ,  G11C16/24 ,  G11C16/08 ,  G11C7/22

Abstract: A data receiving device of a memory device comprises a first pre-amplifier configured to receive previous data, a first reference voltage, and input data, and to output differential signals by comparing the input data with the first reference voltage in response to a clock, when the first pre-amplifier is selected in response to the previous data, a second pre-amplifier configured to receive inverted previous data, a second reference voltage, different from the first reference voltage, and the input data, and outputting a common signal in response to the clock, when the second pre-amplifier is unselected in response to the previous data; and an amplifier configured to receive the differential signals and the common signal, and to latch the input data by amplifying the differential signals.

公开(公告)号：US20210174844A1

公开(公告)日：2021-06-10

申请号：US16930561

申请日：2020-07-16

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jaemin Choi ,  Daehyun Kwon ,  Buyeon Lee

IPC: G11C7/06 ,  G11C7/10 ,  G11C7/22 ,  G11C16/08 ,  G11C16/24

Abstract: A data receiving device of a memory device comprises a first pre-amplifier configured to receive previous data, a first reference voltage, and input data, and to output differential signals by comparing the input data with the first reference voltage in response to a clock, when the first pre-amplifier is selected in response to the previous data, a second pre-amplifier configured to receive inverted previous data, a second reference voltage, different from the first reference voltage, and the input data, and outputting a common signal in response to the clock, when the second pre-amplifier is unselected in response to the previous data; and an amplifier configured to receive the differential signals and the common signal, and to latch the input data by amplifying the differential signals.

公开(公告)号：US12205668B2

公开(公告)日：2025-01-21

申请号：US17722805

申请日：2022-04-18

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jaemin Choi ,  Yonghun Kim ,  Jaewoo Jeong ,  Kyungryun Kim ,  Yoochang Sung ,  Changsik Yoo

IPC: G11C7/10

Abstract: A semiconductor device includes: a plurality of pads connected to a memory device receiving a data signal using first to fourth clock signals having different phases; a data transmission/reception circuit inputting and outputting the data signal to a plurality of data pads of the plurality of pads and including a data delay cell adjusting a phase of the data signal; a clock output circuit outputting first to fourth clock signals to a plurality of clock pads of the plurality of pads and including first to fourth clock delay cells adjusting phases of the first to fourth clock signals; and a controller adjusting a delay amount of at least one of the first to fourth clock delay cells and the data delay cell so that each of the first to fourth clock signals is aligned with the data signal in the memory device.

公开(公告)号：US11804841B2

公开(公告)日：2023-10-31

申请号：US17569041

申请日：2022-01-05

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jaemin Choi ,  Yonghun Kim ,  Jinhyeok Baek ,  Yoochang Sung ,  Changsik Yoo ,  Jeongdon Ihm

IPC: H03K19/003 ,  G11C7/22 ,  G11C5/14 ,  H03K19/0185 ,  G11C7/10 ,  G11C8/06

CPC classification number: H03K19/00384 ,  G11C5/147 ,  G11C7/22 ,  H03K19/018521 ,  G11C7/1057 ,  G11C7/1084 ,  G11C8/06

Abstract: An interface circuit includes: a buffer circuit configured to receive an input signal and to generate an output signal having a delay time, the delay time being determined based on a current level of a bias current and a voltage level of a power supply voltage; and a bias generation circuit configured to vary a voltage level of a bias control voltage so that the delay time is constant by compensating for a change in the voltage level of the power supply voltage, the bias generation circuit being further configured to provide the bias control voltage to the buffer circuit.

公开(公告)号：US20220028434A1

公开(公告)日：2022-01-27

申请号：US17495862

申请日：2021-10-07

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jaemin Choi ,  Daehyun Kwon ,  Buyeon Lee

IPC: G11C7/06 ,  G11C7/10 ,  G11C16/24 ,  G11C16/08 ,  G11C7/22

Abstract: A data receiving device of a memory device comprises a first pre-amplifier configured to receive previous data, a first reference voltage, and input data, and to output differential signals by comparing the input data with the first reference voltage in response to a clock, when the first pre-amplifier is selected in response to the previous data, a second pre-amplifier configured to receive inverted previous data, a second reference voltage, different from the first reference voltage, and the input data, and outputting a common signal in response to the clock, when the second pre-amplifier is unselected in response to the previous data; and an amplifier configured to receive the differential signals and the common signal, and to latch the input data by amplifying the differential signals.

公开(公告)号：US11170825B2

公开(公告)日：2021-11-09

申请号：US16930561

申请日：2020-07-16

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jaemin Choi ,  Daehyun Kwon ,  Buyeon Lee

IPC: G11C7/02 ,  G11C7/06 ,  G11C7/10 ,  G11C16/24 ,  G11C16/08 ,  G11C7/22

Abstract: A data receiving device of a memory device comprises a first pre-amplifier configured to receive previous data, a first reference voltage, and input data, and to output differential signals by comparing the input data with the first reference voltage in response to a clock, when the first pre-amplifier is selected in response to the previous data, a second pre-amplifier configured to receive inverted previous data, a second reference voltage, different from the first reference voltage, and the input data, and outputting a common signal in response to the clock, when the second pre-amplifier is unselected in response to the previous data; and an amplifier configured to receive the differential signals and the common signal, and to latch the input data by amplifying the differential signals.

公开(公告)号：US11948621B2

公开(公告)日：2024-04-02

申请号：US17839639

申请日：2022-06-14

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jaewoo Jeong ,  Yonghun Kim ,  Jaemin Choi ,  Yoochang Sung ,  Changsik Yoo

IPC: G11C11/4076

CPC classification number: G11C11/4076

Abstract: A memory device includes a first rank having first memory banks and a first quad skew adjustment circuit and a second rank having second memory banks and a second quad skew adjustment circuit, wherein each of the first quad skew adjustment circuit and the second quad skew adjustment circuit is configured to: receive a 4-phase clock through first channels; detect internal quad skew of the 4-phase clock; correct skew of the 4-phase clock according to the detected quad skew; and output mode register information corresponding to the detected quad skew through a second channel.

公开(公告)号：US20230035176A1

公开(公告)日：2023-02-02

申请号：US17839639

申请日：2022-06-14

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jaewoo Jeong ,  Yonghun Kim ,  Jaemin Choi ,  Yoochang Sung ,  Changsik Yoo

IPC: G11C11/4076

Abstract: A memory device includes a first rank having first memory banks and a first quad skew adjustment circuit and a second rank having second memory banks and a second quad skew adjustment circuit, wherein each of the first quad skew adjustment circuit and the second quad skew adjustment circuit is configured to: receive a 4-phase clock through first channels; detect internal quad skew of the 4-phase clock; correct skew of the 4-phase clock according to the detected quad skew; and output mode register information corresponding to the detected quad skew through a second channel.