公开(公告)号：US11069399B2

公开(公告)日：2021-07-20

申请号：US16840596

申请日：2020-04-06

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Changbum Kim ,  Sunghoon Kim ,  Seungyeon Kim

IPC: G11C11/408 ,  G11C11/4099 ,  G11C5/02 ,  H01L27/24

Abstract: A memory device including a first memory cell array including first memory cells stacked vertically on a first memory cell array region of a top surface of a substrate; a second memory cell array including second memory cells stacked vertically on a second memory cell array region of the top surface; first word lines coupled to the first memory cells and including a subset of first word lines and remaining first word lines; second word lines coupled to the second memory cells and including a subset of second word lines and remaining second word lines; and a row decoder, including a plurality of merge pass transistors each commonly connected to a respective one of the subset of first word lines and a respective one of the subset of second word lines, disposed in a region of the top surface between the first and second cell array regions.

公开(公告)号：US12062628B2

公开(公告)日：2024-08-13

申请号：US18126996

申请日：2023-03-27

Applicant: Samsung Electronics Co., Ltd.

Inventor： Changbum Kim ,  Sunghoon Kim ,  Daeseok Byeon

IPC: H01L21/00 ,  H01L23/528 ,  H01L23/60 ,  H01L27/092

CPC classification number: H01L23/60 ,  H01L23/528 ,  H01L27/092

Abstract: A semiconductor device includes a gate line extending in a first direction, parallel to an upper surface of a semiconductor substrate; a first active region including a first channel region disposed below the gate line and including a first conductivity-type impurity; a second active region disposed to be separated from the first active region in the first direction, including a second channel region disposed below the gate line, and including the first conductivity-type impurity; and a plurality of metal wirings disposed at a first height level above the semiconductor substrate, wherein at least one metal wiring, among the plurality of metal wirings, is directly electrically connected to the first active region, no metal wirings at the first height level are electrically connected to the second active region, and at least one metal wiring, among the plurality of metal wirings, is connected to receive a signal applied to the gate line.

公开(公告)号：US20230230941A1

公开(公告)日：2023-07-20

申请号：US18126996

申请日：2023-03-27

Applicant: Samsung Electronics Co., Ltd.

Inventor： Changbum Kim ,  Sunghoon Kim ,  Daeseok Byeon

IPC: H01L23/60 ,  H01L23/528 ,  H01L27/092

CPC classification number: H01L23/60 ,  H01L23/528 ,  H01L27/092

Abstract: A semiconductor device includes a gate line extending in a first direction, parallel to an upper surface of a semiconductor substrate; a first active region including a first channel region disposed below the gate line and including a first conductivity-type impurity; a second active region disposed to be separated from the first active region in the first direction, including a second channel region disposed below the gate line, and including the first conductivity-type impurity; and a plurality of metal wirings disposed at a first height level above the semiconductor substrate, wherein at least one metal wiring, among the plurality of metal wirings, is directly electrically connected to the first active region, no metal wirings at the first height level are electrically connected to the second active region, and at least one metal wiring, among the plurality of metal wirings, is connected to receive a signal applied to the gate line.

公开(公告)号：US20220084959A1

公开(公告)日：2022-03-17

申请号：US17218230

申请日：2021-03-31

Applicant: Samsung Electronics Co., Ltd.

Inventor： Changbum Kim ,  Sunghoon Kim ,  Daeseok Byeon

IPC: H01L23/60 ,  H01L27/092 ,  H01L23/528

Abstract: A semiconductor device includes a gate line extending in a first direction, parallel to an upper surface of a semiconductor substrate; a first active region including a first channel region disposed below the gate line and including a first conductivity-type impurity; a second active region disposed to be separated from the first active region in the first direction, including a second channel region disposed below the gate line, and including the first conductivity-type impurity; and a plurality of metal wirings disposed at a first height level above the semiconductor substrate, wherein at least one metal wiring, among the plurality of metal wirings, is directly electrically connected to the first active region, no metal wirings at the first height level are electrically connected to the second active region, and at least one metal wiring, among the plurality of metal wirings, is connected to receive a signal applied to the gate line.

公开(公告)号：US11922997B2

公开(公告)日：2024-03-05

申请号：US17574657

申请日：2022-01-13

Applicant: Samsung Electronics Co., Ltd.

Inventor： Changbum Kim ,  Sunghoon Kim

IPC: G11C16/26 ,  G11C5/06 ,  G11C11/4074 ,  G11C11/4093 ,  G11C11/4094 ,  G11C11/4096 ,  G11C11/4099

CPC classification number: G11C11/4093 ,  G11C5/06 ,  G11C11/4074 ,  G11C11/4094 ,  G11C11/4096 ,  G11C11/4099

Abstract: A non-volatile memory device includes a first semiconductor layer and a second semiconductor layer arranged in the vertical direction. A first semiconductor layer includes a plurality of memory cells, and a plurality of metal lines extending in a first direction, and including first bit lines, second bit lines, and a common source line tapping wire between the first bit lines and the second bit lines. A second semiconductor layer includes a page buffer circuit connected to the first bit lines and the second bit lines, and the page buffer circuit includes first transistors arranged below the first bit lines and electrically connected to the first bit lines, second transistors arranged below the second bit lines and electrically connected to the second bit lines, and a first guard ring arranged below and overlapped the common source line tapping wire in the vertical direction and extending in the first direction.

公开(公告)号：US11637077B2

公开(公告)日：2023-04-25

申请号：US17218230

申请日：2021-03-31

Applicant: Samsung Electronics Co., Ltd.

Inventor： Changbum Kim ,  Sunghoon Kim ,  Daeseok Byeon

IPC: H01L21/00 ,  H01L23/60 ,  H01L23/528 ,  H01L27/092

Abstract: A semiconductor device includes a gate line extending in a first direction, parallel to an upper surface of a semiconductor substrate; a first active region including a first channel region disposed below the gate line and including a first conductivity-type impurity; a second active region disposed to be separated from the first active region in the first direction, including a second channel region disposed below the gate line, and including the first conductivity-type impurity; and a plurality of metal wirings disposed at a first height level above the semiconductor substrate, wherein at least one metal wiring, among the plurality of metal wirings, is directly electrically connected to the first active region, no metal wirings at the first height level are electrically connected to the second active region, and at least one metal wiring, among the plurality of metal wirings, is connected to receive a signal applied to the gate line.

公开(公告)号：US20220320131A1

公开(公告)日：2022-10-06

申请号：US17453228

申请日：2021-11-02

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Changbum Kim ,  Sunghoon Kim

IPC: H01L27/11575 ,  H01L27/11548 ,  H01L27/11556 ,  H01L27/11529 ,  H01L27/11582 ,  H01L27/11573 ,  G11C16/04 ,  G11C16/24

Abstract: A semiconductor device includes a plurality of semiconductor elements, each of the plurality of semiconductor elements including an active region disposed on a substrate, and a gate structure intersecting the active region and extending in a first direction that is parallel to an upper surface of the substrate; and at least one dummy element disposed between a pair of semiconductor elements adjacent to each other in a second direction, intersecting the first direction, among the plurality of semiconductor elements. The dummy element includes a dummy active region and at least one dummy gate structure intersecting the dummy active region and extending in the first direction. A length of the dummy active region in the second direction is less than a length of the active region included in each of the pair of semiconductor elements.