公开(公告)号：US12300668B2

公开(公告)日：2025-05-13

申请号：US17889053

申请日：2022-08-16

Applicant: Samsung Electronics Co., Ltd.

Inventor： Raehyung Do ,  Seunghyun Go ,  Jungsik Lee ,  Jongho Lee ,  Younghun Cheong ,  Cheolsoo Han

IPC: H01L25/065 ,  H01L23/00 ,  H01L23/31 ,  H01L23/498

Abstract: A semiconductor package comprising a substrate including substrate pads on a top surface thereof, a first upper semiconductor chip on the substrate and including conductive chip pads, and bonding wires coupled to the substrate pads and the first upper semiconductor chip. The bonding wires include first and second bonding wires. The substrate has a first region between the conductive chip pads and the substrate pads, and a second region between the first region and the substrate pads. The second bonding wire has a maximum vertical level on the first region of the substrate. On the first region of the substrate, the first bonding wire is at a level higher than that of the second bonding wire. On the second region of the substrate, the second bonding wire is at a level higher than that of the first bonding wire.

公开(公告)号：US12100635B2

公开(公告)日：2024-09-24

申请号：US17185116

申请日：2021-02-25

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sanghoon Jung ,  Young Lyong Kim ,  Cheolsoo Han

IPC: H01L23/31 ,  H01L21/56 ,  H01L23/00 ,  H01L23/498 ,  H01L25/18 ,  H01L23/48

CPC classification number: H01L23/3157 ,  H01L21/563 ,  H01L23/49833 ,  H01L23/49838 ,  H01L24/32 ,  H01L24/83 ,  H01L25/18 ,  H01L23/481 ,  H01L23/49816 ,  H01L23/49822 ,  H01L24/92 ,  H01L2224/32054 ,  H01L2224/32057 ,  H01L2224/32225 ,  H01L2224/83939 ,  H01L2224/92125

Abstract: Disclosed is a semiconductor package comprising a lower substrate including a conductive line; a first semiconductor chip on the lower substrate; an under-fill layer between the first semiconductor chip and the lower substrate, the under-fill layer including a central part below the first semiconductor chip and an edge part isolated from direct contact with the central part in a first direction parallel to a top surface of the lower substrate, and a recess region between the central part and the edge part. The recess region may be defined by a sidewall of the central part, a sidewall of the edge part, and a top surface of the conductive line in the lower substrate.