公开(公告)号：US12159858B2

公开(公告)日：2024-12-03

申请号：US17568361

申请日：2022-01-04

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hyunsoo Chung ,  Young Lyong Kim ,  Inhyo Hwang

IPC: H01L25/065 ,  H01L23/00 ,  H01L23/31 ,  H01L23/498 ,  H01L25/00

Abstract: A semiconductor package includes a first semiconductor chip on a substrate, a buried solder ball on the substrate and spaced apart from the first semiconductor chip, a first molding layer on the substrate and encapsulating and exposing the first semiconductor chip and the buried solder ball, a second semiconductor chip on the first molding layer and vertically overlapping the buried solder ball and a portion of the first semiconductor chip, and a second molding layer on the first molding layer and covering the second semiconductor chip. The second semiconductor chip is supported on the first semiconductor chip through a dummy solder ball between the first and second semiconductor chips. The second semiconductor chip is connected to the buried solder ball through a signal solder ball between the buried solder ball and the second semiconductor chip.

公开(公告)号：US20240032311A1

公开(公告)日：2024-01-25

申请号：US18180188

申请日：2023-03-08

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hyunsoo Chung ,  Young Lyong Kim ,  Inhyo Hwang

IPC: H10B80/00 ,  H10B41/27 ,  H10B43/27

CPC classification number: H10B80/00 ,  H10B41/27 ,  H10B43/27

Abstract: A semiconductor device includes a peripheral circuit structure including peripheral circuits on a substrate and first bonding pads electrically connected to the peripheral circuits and a cell array structure including memory cells on a semiconductor layer and second bonding pads electrically connected to the memory cells and bonded to the first bonding pads. The cell array structure includes a stacked structure including insulating layers and electrodes, an external connection pad on a surface of the semiconductor layer, a dummy pattern at a same level as the semiconductor layer relative to the substrate, and a photosensitive insulating layer on the semiconductor layer and the dummy pattern. A first thickness of a portion of the photosensitive insulating layer vertically overlapping the external connection pad is greater than a second thickness of another portion of the photosensitive insulating layer vertically overlapping the dummy pattern.

公开(公告)号：US20230047345A1

公开(公告)日：2023-02-16

申请号：US17680617

申请日：2022-02-25

Applicant: SAMSUNG ELECTRONICS CO.,LTD.

Inventor： Inhyo HWANG ,  Young Lyong Kim

IPC: H01L25/065 ,  H01L23/498

Abstract: Provided is a semiconductor package including a first semiconductor chip provided on a package substrate, an interconnection substrate provided on the package substrate, the interconnection substrate having a side surface facing the first semiconductor chip, and a second semiconductor chip provided on the interconnection substrate and extended to a region on a top surface of the first semiconductor chip, wherein the interconnection substrate includes a lower interconnection layer facing the package substrate, an upper interconnection layer facing the first semiconductor chip, and a passive device between the lower interconnection layer and the upper interconnection layer, and wherein the passive device is electrically connected to the second semiconductor chip.

公开(公告)号：US11488894B2

公开(公告)日：2022-11-01

申请号：US17071137

申请日：2020-10-15

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Young Lyong Kim ,  Seungduk Baek

IPC: H01L23/488 ,  H01L23/538 ,  H01L23/00

Abstract: A semiconductor device includes a semiconductor substrate divided into a pad region and a cell region and having an active surface and an inactive surface opposite to the active surface, a plurality of metal lines on the active surface of the semiconductor substrate, passivation layers on the active surface of the semiconductor substrate, and a plurality of bumps in the cell region. The passivation layers include a first passivation layer covering the plurality of metal lines and having a non-planarized top surface along an arrangement profile of the plurality of metal lines, and a second passivation layer on the non-planarized top surface of the first passivation layer and having a planarized top surface on which the plurality of bumps are disposed.

公开(公告)号：US20240332200A1

公开(公告)日：2024-10-03

申请号：US18737527

申请日：2024-06-07

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Young Lyong Kim ,  Hyunsoo Chung ,  Inhyo Hwang

IPC: H01L23/538 ,  H01L23/31 ,  H01L25/065

CPC classification number: H01L23/5385 ,  H01L23/3114 ,  H01L23/5384 ,  H01L23/5386 ,  H01L25/0655

Abstract: A semiconductor package includes a package substrate with a first vent hole, a first semiconductor chip mounted the package substrate, an interposer including supporters on a bottom surface of the interposer and a second vent hole, wherein the supporters contact a top surface of the first semiconductor chip, and the interposer is electrically connected to the package substrate through connection terminals. The semiconductor package further include a second semiconductor chip mounted on the interposer, and a molding layer disposed on the package substrate to cover the first semiconductor chip, the interposer, and the second semiconductor chip.

公开(公告)号：US11830853B2

公开(公告)日：2023-11-28

申请号：US17582079

申请日：2022-01-24

Applicant: Samsung Electronics Co., Ltd.

Inventor： Ae-Nee Jang ,  Young Lyong Kim

IPC: H01L25/065 ,  H01L23/31

CPC classification number: H01L25/0657 ,  H01L23/3107 ,  H01L25/0652 ,  H01L2224/09181 ,  H01L2225/06506 ,  H01L2225/06517 ,  H01L2225/06562

Abstract: Semiconductor devices may include a first semiconductor chip, a first redistribution layer on a bottom surface of the first semiconductor chip, a second semiconductor chip on the first semiconductor chip, a second redistribution layer on a bottom surface of the second semiconductor chip, a mold layer extending on sidewalls of the first and second semiconductor chips and on the bottom surface of the first semiconductor chip, and an external terminal extending through the mold layer and electrically connected to the first redistribution layer. The second redistribution layer may include an exposed portion. The first redistribution layer may include a first conductive pattern electrically connected to the first semiconductor chip and a second conductive pattern electrically insulated from the first semiconductor chip. The exposed portion of the second redistribution layer and the second conductive pattern of the first redistribution layer may be electrically connected by a first connection wire.

公开(公告)号：US11257793B2

公开(公告)日：2022-02-22

申请号：US16946199

申请日：2020-06-10

Applicant: Samsung Electronics Co., Ltd.

Inventor： Ae-Nee Jang ,  Young Lyong Kim

IPC: H01L25/065 ,  H01L23/31

Abstract: Semiconductor devices may include a first semiconductor chip, a first redistribution layer on a bottom surface of the first semiconductor chip, a second semiconductor chip on the first semiconductor chip, a second redistribution layer on a bottom surface of the second semiconductor chip, a mold layer extending on sidewalls of the first and second semiconductor chips and on the bottom surface of the first semiconductor chip, and an external terminal extending through the mold layer and electrically connected to the first redistribution layer. The second redistribution layer may include an exposed portion. The first redistribution layer may include a first conductive pattern electrically connected to the first semiconductor chip and a second conductive pattern electrically insulated from the first semiconductor chip. The exposed portion of the second redistribution layer and the second conductive pattern of the first redistribution layer may be electrically connected by a first connection wire.

公开(公告)号：US20190229091A1

公开(公告)日：2019-07-25

申请号：US16225074

申请日：2018-12-19

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Taehyeong KIM ,  Young Lyong Kim ,  Geol Nam

IPC: H01L25/065 ,  H01L23/00 ,  H01L21/56 ,  H01L23/31

Abstract: Disclosed are semiconductor packages and methods of manufacturing the same. The method of manufacturing a semiconductor package may include providing a carrier substrate having a trench formed on a first top surface of the carrier substrate, providing a first semiconductor chip on the carrier substrate, mounting at least one second semiconductor chip on a second top surface of the first semiconductor chip, coating a mold member to surround a first lateral surface of the first semiconductor chip and a second lateral surface of the at least one second semiconductor chip, and curing the mold member to form a mold layer. The trench may be provided along a first edge of the first semiconductor chip. The mold member may cover a second edge of a bottom surface the first semiconductor chip.

公开(公告)号：US10177131B2

公开(公告)日：2019-01-08

申请号：US15442001

申请日：2017-02-24

Applicant: Samsung Electronics Co., Ltd.

Inventor： Young Lyong Kim ,  Jin-woo Park ,  Choongbin Yim ,  Younji Min

IPC: H01L25/00 ,  H01L23/538 ,  H01L23/31 ,  H01L23/29 ,  H01L23/00 ,  H01L25/10 ,  H01L25/065 ,  H01L21/56

Abstract: Provided are a semiconductor package and a method of manufacturing the same. The semiconductor package comprises a substrate, a semiconductor chip on the substrate, an interconnect substrate spaced apart from the semiconductor chip on the substrate and including a conductive member therein, a solder ball on the interconnect substrate and electrically connected to the conductive member, a polymer layer on the interconnect substrate and the semiconductor chip and including an opening through which the solder ball is exposed, and polymer particles in the solder ball and including the same material as the polymer layer.

公开(公告)号：US20250054915A1

公开(公告)日：2025-02-13

申请号：US18930667

申请日：2024-10-29

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hyunsoo Chung ,  Young Lyong Kim ,  Inhyo Hwang

IPC: H01L25/065 ,  H01L23/00 ,  H01L23/31 ,  H01L23/498 ,  H01L25/00

Abstract: A semiconductor package includes a first semiconductor chip on a substrate, a buried solder ball on the substrate and spaced apart from the first semiconductor chip, a first molding layer on the substrate and encapsulating and exposing the first semiconductor chip and the buried solder ball, a second semiconductor chip on the first molding layer and vertically overlapping the buried solder ball and a portion of the first semiconductor chip, and a second molding layer on the first molding layer and covering the second semiconductor chip. The second semiconductor chip is supported on the first semiconductor chip through a dummy solder ball between the first and second semiconductor chips. The second semiconductor chip is connected to the buried solder ball through a signal solder ball between the buried solder ball and the second semiconductor chip.