公开(公告)号：US20170222633A1

公开(公告)日：2017-08-03

申请号：US15399146

申请日：2017-01-05

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jong Woo KIM ,  Min Su KIM ,  Ah Reum KIM ,  Chung Hee KIM

IPC: H03K3/3562 ,  H03K3/037

Abstract: Provided is a semiconductor device including low power retention flip-flop. The semiconductor device includes a first line to which a global power supply voltage is applied, a second line to which a local power supply voltage is applied, the second line being separated from the first line, a first operating circuit connected to the second line to use the local power supply voltage, a first power gating circuit determining whether the local power supply voltage is applied to the first operating circuit and a first retention flip-flop connected to the first line and the second line, wherein the first retention flip-flop comprises a first circuit including a master latch, a second circuit including a slave latch, and a first tri-state inverter connected between the master latch and the slave latch.