公开(公告)号：US20230074317A1

公开(公告)日：2023-03-09

申请号：US17696551

申请日：2022-03-16

Applicant: Samsung Electronics Co., Ltd.

Inventor： Ki Won KIM ,  Sung Hoon KIM ,  Ah Reum KIM

IPC: H01L27/11573 ,  H01L23/522 ,  H01L23/00 ,  H01L25/065 ,  H01L25/18 ,  H01L27/11529

Abstract: A semiconductor memory device including a memory cell array and a peripheral circuit element configured to control an operation of the memory cell array, and a wiring structure including first and second wiring structures spaced apart from each other on the peripheral circuit element, a first voltage and a second voltage different from the first voltage applied to two opposite ends of the first wiring structure, respectively, and a third voltage different from the first and second voltages applied to the second wiring structure, may be provided. The first wiring structure includes first lines extended in a first direction and spaced apart from each other in a second direction crossing the first direction, the second wiring structure includes second lines extended in the first direction and spaced apart from each other in the second direction, and one of the first lines is between the second lines.

公开(公告)号：US20210119617A1

公开(公告)日：2021-04-22

申请号：US16866941

申请日：2020-05-05

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hyun LEE ,  Min Su KIM ,  Ah Reum KIM

IPC: H03K3/3562 ,  H01L23/528 ,  H01L27/02

Abstract: A semiconductor device is provided. The semiconductor device includes a clock gate line supplying a clock signal, an inverted clock gate line disposed in parallel to the clock gate line and supplying an inverted clock signal, a first latch circuit performing a first latch operation based on the clock signal and the inverted clock signal and a second latch circuit disposed on a side of the first latch circuit in a first direction, receiving an output of the first latch circuit, and operating based on the clock signal and the inverted clock, wherein the clock gate line and the inverted clock gate line extend in the first direction and are shared by the first and second latch circuits.

公开(公告)号：US20170222633A1

公开(公告)日：2017-08-03

申请号：US15399146

申请日：2017-01-05

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jong Woo KIM ,  Min Su KIM ,  Ah Reum KIM ,  Chung Hee KIM

IPC: H03K3/3562 ,  H03K3/037

Abstract: Provided is a semiconductor device including low power retention flip-flop. The semiconductor device includes a first line to which a global power supply voltage is applied, a second line to which a local power supply voltage is applied, the second line being separated from the first line, a first operating circuit connected to the second line to use the local power supply voltage, a first power gating circuit determining whether the local power supply voltage is applied to the first operating circuit and a first retention flip-flop connected to the first line and the second line, wherein the first retention flip-flop comprises a first circuit including a master latch, a second circuit including a slave latch, and a first tri-state inverter connected between the master latch and the slave latch.