公开(公告)号：US20220020438A1

公开(公告)日：2022-01-20

申请号：US17195824

申请日：2021-03-09

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jun-Ho SEO ,  Jung Ho LEE ,  Dae Sik HAM ,  Gi Baek KIM ,  Sang Yong YOON ,  Won-Taeck JUNG

IPC: G11C16/30 ,  G11C16/10 ,  G11C16/26 ,  G11C16/04 ,  G11C16/08

Abstract: A non-volatile memory device including: a first string including a first string select transistor, a first memory cell and a first ground select transistor, a second string including a second string select transistor, a second memory cell and a second ground select transistor, and a controller to apply a pass voltage to a first string select line from a first time, apply a first read voltage to a first word line during a first read section from the first time to a second time, apply a first ground select line voltage to a first ground select line from the first time, apply a ground voltage to a second string select line, apply the first ground select line voltage to a second ground select line during a first control section, and apply a first common source line voltage to a common source line during the first control section.

公开(公告)号：US20240145017A1

公开(公告)日：2024-05-02

申请号：US18364126

申请日：2023-08-02

Applicant: Samsung Electronics Co., Ltd.

Inventor： Dae Sik HAM ,  Yong-Wan SON ,  Sang-Hyun JOO

IPC: G11C16/34 ,  G11C16/16 ,  G11C16/22

CPC classification number: G11C16/3495 ,  G11C16/16 ,  G11C16/22

Abstract: Disclosed is a memory device which a memory cell array including a plurality of memory blocks, a voltage generator configured to generate an erase voltage and row line voltages to be provided to a target block from among the plurality of memory blocks, in which an erase operation is to be performed, and control logic configured to control the memory cell array and the voltage generator. The voltage generator is configured to provide the erase voltage to at least one of a bit line and a common source line connected with the target block and to provide the row line voltages to row lines connected with the target block, and the control logic is configured to change a slope of the erase voltage and a floating time of at least one row line among the row lines depending on a program/erase cycle.

公开(公告)号：US20250157542A1

公开(公告)日：2025-05-15

申请号：US18810861

申请日：2024-08-21

Applicant: Samsung Electronics Co., Ltd.

Inventor： Dae Sik HAM ,  ByeongChan KO ,  Sanghun KIM

IPC: G11C16/10 ,  G11C16/04 ,  G11C16/08 ,  G11C16/34 ,  H10B43/27 ,  H10B43/35

Abstract: A method of programming a non-volatile memory device which includes a first cell string and a second cell string connected to a same bit line and sharing a first ground selection line, and a third cell string and a fourth cell string connected to the same bit line and sharing a second ground selection line, includes performing a ground separate initial precharge operation, in which a first voltage is applied to the first ground selection line and a second voltage is applied to the second ground selection line, based on the first cell string being selected as a selected cell string, performing a program voltage applying operation in which a program voltage is applied to a word line selected as a selected word line from among a plurality of word lines, and performing a verify operation in which a verify voltage is applied to the selected word line.