公开(公告)号：US20240004572A1

公开(公告)日：2024-01-04

申请号：US18202692

申请日：2023-05-26

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sang-Hyun JOO

IPC: G06F3/06

CPC classification number: G06F3/0652 ,  G06F3/0604 ,  G06F3/0679

Abstract: In some embodiments, a non-volatile memory device includes a control logic circuit configured to generate a program signal and an erase signal based on control signals, a voltage generator configured to generate a program voltage and an erase voltage based on the program signal and the erase signal, a memory cell array including a memory cell, a string select transistor coupled to the memory cell, a bit-line coupled to the string select transistor, and a string select line coupled to the string select transistor, and a page buffer circuit coupled to the bit-line, and including a first precharge transistor that is configured to operate based on the program signal and the erase signal. The first precharge transistor is configured to apply the program voltage and the erase voltage to the bit-line in response to the program signal and the erase signal, respectively.

公开(公告)号：US20210312989A1

公开(公告)日：2021-10-07

申请号：US17126933

申请日：2020-12-18

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jae-Hak YUN ,  Jae Woo IM ,  Sang-Hyun JOO

IPC: G11C16/08 ,  G11C16/04

Abstract: A nonvolatile memory device and an operating method are provided. The nonvolatile memory device includes a memory cell array including a plurality of planes, each plane including a plurality of memory blocks, an address decoder connected to the memory cell array, a voltage generator configured to apply an operating voltage to the address decoder, a page buffer circuit including page buffers corresponding to each of the planes, a data input/output circuit connected to the page buffer circuit configured to input and output data and a control unit configured to control the operation of the address decoder, the voltage generator, the page buffer circuit, and the data input/output circuit, wherein the control unit is configured to operate in a multi-operation or a single operation by checking whether a memory block of an access address is a bad block.

公开(公告)号：US20210233597A1

公开(公告)日：2021-07-29

申请号：US17026713

申请日：2020-09-21

Applicant: Samsung Electronics Co., Ltd.

Inventor： Myoung-Won YOON ,  Jae-Hak YUN ,  Jae Woo IM ,  Sang-Hyun JOO

IPC: G11C16/34 ,  G11C16/08 ,  G11C16/16 ,  G11C16/26 ,  G11C16/30

Abstract: A nonvolatile memory device includes processing circuitry configured to apply a sub-voltage to the first word lines, determine a desired first read voltage based on a threshold voltage distribution of a plurality of first memory cells connected to the first word lines, apply the sub-voltage to the second word lines, determine a desired second read voltage based on a threshold voltage distribution of a plurality of second memory cells connected to the second word lines, apply the desired first read voltage to the first word lines while simultaneously reading the first memory cells connected to the first word lines, and apply the desired second read voltage different from the desired first read voltage to the second word lines while simultaneously reading the second memory cells connected to the second word lines.

公开(公告)号：US20140056078A1

公开(公告)日：2014-02-27

申请号：US14071020

申请日：2013-11-04

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sang-Hyun JOO

IPC: G11C16/30

CPC classification number: G11C16/10 ,  G11C11/5628 ,  G11C16/0483 ,  G11C16/30 ,  G11C16/3404 ,  G11C16/3454 ,  G11C16/3459

Abstract: A non-volatile memory device is provided. The non-volatile memory device includes a cell string including a plurality of non-volatile memory cells; and an operation control block configured to supply a program voltage to a word line connected to a selected non-volatile memory cell among the plurality of non-volatile memory cells during a program operation, configured to supply a first negative voltage to the word line during a detrapping operation, and configured to supply a second negative voltage as a verify voltage to the word line during a program verify operation.

Abstract translation: 提供了一种非易失性存储器件。 非易失性存储器件包括包括多个非易失性存储器单元的单元串; 以及操作控制块，其被配置为在编程操作期间向连接到所述多个非易失性存储单元中的所选择的非易失性存储单元的字线提供编程电压，用于在编程期间向所述字线提供第一负电压 取样操作，并且被配置为在程序验证操作期间将第二负电压作为验证电压提供给字线。

公开(公告)号：US20240145017A1

公开(公告)日：2024-05-02

申请号：US18364126

申请日：2023-08-02

Applicant: Samsung Electronics Co., Ltd.

Inventor： Dae Sik HAM ,  Yong-Wan SON ,  Sang-Hyun JOO

IPC: G11C16/34 ,  G11C16/16 ,  G11C16/22

CPC classification number: G11C16/3495 ,  G11C16/16 ,  G11C16/22

Abstract: Disclosed is a memory device which a memory cell array including a plurality of memory blocks, a voltage generator configured to generate an erase voltage and row line voltages to be provided to a target block from among the plurality of memory blocks, in which an erase operation is to be performed, and control logic configured to control the memory cell array and the voltage generator. The voltage generator is configured to provide the erase voltage to at least one of a bit line and a common source line connected with the target block and to provide the row line voltages to row lines connected with the target block, and the control logic is configured to change a slope of the erase voltage and a floating time of at least one row line among the row lines depending on a program/erase cycle.

公开(公告)号：US20220139470A1

公开(公告)日：2022-05-05

申请号：US17580062

申请日：2022-01-20

Applicant: Samsung Electronics Co., Ltd.

Inventor： Myoung-Won YOON ,  Sang-Hyun JOO

IPC: G11C16/34 ,  G11C16/04 ,  G11C16/16 ,  G11C16/28 ,  G11C16/10

Abstract: A nonvolatile memory device includes a memory block with an unused line connected to dummy cells and used lines connected to normal cells, and a controller which applies an erase voltage to the memory block, applies an unused line erase voltage to the unused line, and applies a word line erase voltage to the used lines during an erase operation. The dummy cells are not programmed during a program operation while the normal cells are programmed, the unused line erase voltage transits from a first voltage to a floating voltage at a first time point, and the controller reads the dummy cells and controls at least one of the magnitude of the first voltage and the first time point based on the result of reading the dummy cells.

公开(公告)号：US20220093206A1

公开(公告)日：2022-03-24

申请号：US17319493

申请日：2021-05-13

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sang-Hyun JOO ,  Tae-Min PARK ,  Hyungsoo KIM ,  Jaewoo IM ,  Won-Taeck JUNG

IPC: G11C29/50 ,  G11C16/04 ,  G11C16/08 ,  G11C16/10 ,  G11C16/24 ,  G11C16/34 ,  H01L27/11556 ,  H01L27/11582 ,  H01L25/065 ,  H01L25/18 ,  H01L23/00

Abstract: Disclosed is a nonvolatile memory device, which includes a memory cell array including cell strings, a row decoder connected with a ground selection transistor of each of the cell strings through a ground selection line, connected with memory cells of each of the cell strings through word lines, and connected with a string selection transistor of each of the cell strings through a string selection line, and a page buffer connected with the cell strings through bit lines. In a first period of a check operation, the page buffer applies a first bias voltage to the bit lines, and the row decoder applies a turn-off voltage to the ground selection line, a turn-on voltage to the string selection line, and a first check voltage to the word lines. In a second period of the check operation, the page buffer senses first changes of voltages of the bit lines.

公开(公告)号：US20210225452A1

公开(公告)日：2021-07-22

申请号：US17035188

申请日：2020-09-28

Applicant: Samsung Electronics Co., Ltd.

Inventor： Myoung-Won YOON ,  Sang-Hyun JOO

IPC: G11C16/34 ,  G11C16/04 ,  G11C16/10 ,  G11C16/16 ,  G11C16/28

Abstract: A nonvolatile memory device includes a memory block with an unused line connected to dummy cells and used lines connected to normal cells, and a controller which applies an erase voltage to the memory block, applies an unused line erase voltage to the unused line, and applies a word line erase voltage to the used lines during an erase operation. The dummy cells are not programmed during a program operation while the normal cells are programmed, the unused line erase voltage transits from a first voltage to a floating voltage at a first time point, and the controller reads the dummy cells and controls at least one of the magnitude of the first voltage and the first time point based on the result of reading the dummy cells.

公开(公告)号：US20150138889A1

公开(公告)日：2015-05-21

申请号：US14597064

申请日：2015-01-14

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sang-Hyun JOO

IPC: G11C16/10 ,  G11C16/34

CPC classification number: G11C16/10 ,  G11C11/5628 ,  G11C16/0483 ,  G11C16/30 ,  G11C16/3404 ,  G11C16/3454 ,  G11C16/3459

Abstract: A non-volatile memory device is provided. The non-volatile memory device includes a cell string including a plurality of non-volatile memory cells; and an operation control block configured to supply a program voltage to a word line connected to a selected non-volatile memory cell among the plurality of non-volatile memory cells during a program operation, configured to supply a first negative voltage to the word line during a detrapping operation, and configured to supply a second negative voltage as a verify voltage to the word line during a program verify operation.

Abstract translation: 提供了一种非易失性存储器件。 非易失性存储器件包括包括多个非易失性存储器单元的单元串; 以及操作控制块，其被配置为在编程操作期间向连接到所述多个非易失性存储单元中的所选择的非易失性存储单元的字线提供编程电压，用于在编程期间向所述字线提供第一负电压 取样操作，并且被配置为在程序验证操作期间将第二负电压作为验证电压提供给字线。

公开(公告)号：US20130336071A1

公开(公告)日：2013-12-19

申请号：US13913710

申请日：2013-06-10

Applicant: Samsung Electronics Co., Ltd

Inventor： Ohsuk KWON ,  Sang-Hyun JOO ,  HyeongJun KIM ,  Kitae PARK ,  Seung-Hwan SHIN

IPC: G11C16/10

CPC classification number: G11C16/10 ,  G11C16/24 ,  G11C16/3459

Abstract: A nonvolatile memory device includes a memory cell array including a plurality of memory cells, a page buffer circuit connected with the memory cell array via a plurality of bit lines and configured to selectively pre-charge the plurality of bit lines, and control logic configured to control the page buffer circuit such that a pre-charge voltage is applied to selected bit lines of the plurality of bit lines during a first time at a read operation and such that a pre-charge voltage is applied to selected bit lines of the plurality of bit lines during a second time different from the first time at a verification read operation. The second time is determined on the basis of the number of selected bit lines of the plurality of bit lines at the verification read operation.

Abstract translation: 非易失性存储器件包括包括多个存储器单元的存储单元阵列，经由多个位线与存储单元阵列连接并被配置为选择性地预充电多个位线的页缓冲器电路，以及配置为 控制页面缓冲器电路，使得在读取操作的第一时间期间将预充电电压施加到多个位线的选定位线，并且使得预充电电压被施加到多个位线中的选定位线 在第二时间不同于在验证读取操作的第一时间的位线。 基于在验证读取操作中的多个位线的选定位线的数量来确定第二次。