公开(公告)号：US20240404570A1

公开(公告)日：2024-12-05

申请号：US18581187

申请日：2024-02-19

Applicant: Samsung Electronics Co., Ltd.

Inventor： Ki-Seok PARK ,  Do-Han KIM ,  Minsu BAE ,  Chang-Hyun BAE ,  Young-Hoon SON ,  Hye-Seung YU ,  Yoenhwa LEE ,  Daihyun LIM ,  Insu CHOI ,  Kideok HAN

IPC: G11C7/22 ,  G11C7/10

Abstract: A method of training a memory device is provided. In first to third DCA training steps, a score for each of first to third DCA code combinations is calculated based on an eye window size of a data signal, and in response to a tie occurring among scores, a DCA code combination is selected based on the sum of an even-eye window minimum value and an odd-eye window minimum value of the data signal.

公开(公告)号：US20220215866A1

公开(公告)日：2022-07-07

申请号：US17480359

申请日：2021-09-21

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yong Jun YU ,  Nam Hyung KIM ,  Do-Han KIM ,  Min Su KIM ,  Deok Ho SEO ,  Won Jae SHIN ,  Chang Min LEE ,  Il Gyu JUNG ,  In Su CHOI

IPC: G11C7/10 ,  G11C7/22

Abstract: A semiconductor device including a memory device which has improved reliability is provided. The semiconductor device comprises at least one data pin configured to transfer a data signal, at least one command address pin configured to transfer a command and an address, at least one serial pin configured to transfer a serial data signal, and processing circuitry connected to the at least one data pin and the at least one serial pin. The processing circuitry is configured to receive the data signal from outside through the at least one data pin, and the processing circuitry is configured to output the serial data signal through the at least one serial pin in response to the received data signal.

公开(公告)号：US20210026567A1

公开(公告)日：2021-01-28

申请号：US16814281

申请日：2020-03-10

Applicant: Samsung Electronics Co., Ltd.

Inventor： Seung-Woo LIM ,  Kyu-Min PARK ,  Do-Han KIM

IPC: G06F3/06 ,  G06F12/10

Abstract: A storage system includes a processor configured to request a write operation of first data corresponding to a first logical address, and requests a write operation of second data corresponding to a second logical address, a memory module including a nonvolatile memory device configured to store the first data and the second data, and a controller configured to convert the first logical address into a first device logical address, and converts the second logical address into a second device logical address based on the first device logical address and a size of the first data, and a storage device configured to store the first data in the storage device based on the first device logical address, and store the second data in the storage device based on the second device logical address.

公开(公告)号：US20200221103A1

公开(公告)日：2020-07-09

申请号：US16631347

申请日：2018-07-11

Applicant: Samsung Electronics Co., Ltd

Inventor： Do-Han KIM ,  Jin-Min BANG ,  Chang-Woo LEE

IPC: H04N19/167 ,  H04N5/232 ,  H04N19/17 ,  G06K9/78

Abstract: According to one embodiment of the present invention, an electronic device may comprise a processor and an image sensing module, wherein the image sensing module comprises an image sensor, and a control circuit electrically connected to the image sensor and connected to the processor through an interface, and the control circuit is configured to: acquire at least one raw image, using the image sensor; designate, for the at least one raw image, first data corresponding to a first region and second data not corresponding to the first region, on the basis of information related to the first region in the at least one raw image; transform the at least one raw image by changing at least a part of the second data to a designated value; and compress the at least one transformed raw image and transmit the compressed transformed raw image to the processor.

公开(公告)号：US20240321338A1

公开(公告)日：2024-09-26

申请号：US18529283

申请日：2023-12-05

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kideok HAN ,  Ki-Seok PARK ,  Young-Hoon SON ,  Do-Han KIM ,  Min-Su BAE ,  Yoenhwa LEE ,  Insu CHOI

IPC: G11C11/4076 ,  G11C11/4096

CPC classification number: G11C11/4076 ,  G11C11/4096

Abstract: A training method of a memory device adjusting an eye window of a data signal in response to a duty cycle adjuster (DCA) includes performing a first training operation that selects a first DCA code corresponding to a first internal clock signal having a phase difference of 180° relative to a reference internal clock signal, and performing a second training operation that selects a second DCA code and a third DCA code respectively corresponding to a second internal clock signal and a third internal clock signal having a phase difference of 90° and 270° relative to reference internal clock signal. In the first training operation, the eye window size of the data signal is measured in units of two unit intervals, and in the second training operation, the eye window size of the data signal is measured in units of one unit interval.

公开(公告)号：US20230112776A1

公开(公告)日：2023-04-13

申请号：US17889117

申请日：2022-08-16

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Dae-Jeong KIM ,  Tae-Kyeong KO ,  Nam Hyung KIM ,  Do-Han KIM ,  Deokho SEO ,  Ho-Young LEE ,  Insu CHOI

IPC: G06F3/06

Abstract: An operation method of a memory controller, which is configured to control a memory module including a plurality of memory devices and at least one error correction code (ECC) device, is provided. The method includes reading a data set including user data stored in the plurality of memory devices and ECC data stored in the at least one ECC device, based on a read command and a first address, and writing uncorrectable data in a memory area, which is included in each of the plurality of memory devices and the at least one ECC device and corresponds to the first address, when an error of the user data is not corrected based on the ECC data.