公开(公告)号：US20240015970A1

公开(公告)日：2024-01-11

申请号：US18372885

申请日：2023-09-26

Applicant: Samsung Electronics Co., Ltd.

Inventor： Woosung Yang ,  HOJUN SEONG ,  JOONHEE LEE ,  JOON-SUNG LIM ,  EUNTAEK JUNG

IPC: H10B43/27 ,  H01L23/522 ,  H10B41/10 ,  H10B41/27 ,  H10B41/46 ,  H10B43/10 ,  H10B43/40

CPC classification number: H10B43/27 ,  H01L23/5226 ,  H10B41/10 ,  H10B41/27 ,  H10B41/46 ,  H10B43/10 ,  H10B43/40

Abstract: Disclosed is a semiconductor memory device comprising a second substrate on a first substrate and including a lower semiconductor layer and an upper semiconductor layer on the lower semiconductor layer, an electrode structure on the upper semiconductor layer and including a plurality of stacked electrodes, a vertical channel structure that penetrates the electrode structure and is connected to the second substrate, an interlayer dielectric layer that covers the electrode structure, and a cutting structure that penetrates the interlayer dielectric layer and the upper semiconductor layer. The upper semiconductor layer has a first sidewall defined by the cutting structure. The lower semiconductor layer has a second sidewall adjacent to the first sidewall. The first sidewall and the second sidewall are horizontally offset from each other.

公开(公告)号：US20210225870A1

公开(公告)日：2021-07-22

申请号：US17026377

申请日：2020-09-21

Applicant: Samsung Electronics Co., Ltd.

Inventor： WOOSUNG YANG ,  HOJUN SEONG ,  JOONHEE LEE ,  JOON-SUNG LIM ,  EUNTAEK JUNG

IPC: H01L27/11582 ,  H01L27/11565 ,  H01L23/522 ,  H01L27/11573 ,  H01L27/11519 ,  H01L27/11556 ,  H01L27/11539

Abstract: Disclosed is a semiconductor memory device comprising a second substrate on a first substrate and including a lower semiconductor layer and an upper semiconductor layer on the lower semiconductor layer, an electrode structure on the upper semiconductor layer and including a plurality of stacked electrodes, a vertical channel structure that penetrates the electrode structure and is connected to the second substrate, an interlayer dielectric layer that covers the electrode structure, and a cutting structure that penetrates the interlayer dielectric layer and the upper semiconductor layer. The upper semiconductor layer has a first sidewall defined by the cutting structure. The lower semiconductor layer has a second sidewall adjacent to the first sidewall. The first sidewall and the second sidewall are horizontally offset from each other.