中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

25 records (took 0.016 seconds)

    Three-dimensional semiconductor memory device
    3.
    发明授权
    Three-dimensional semiconductor memory device 有权

    公开(公告)号：US11296102B2

    公开(公告)日：2022-04-05

    申请号：US16858983

    申请日：2020-04-27

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Sung-Min Hwang ,  Woosung Yang ,  Joon-Sung Lim ,  Jiyoung Kim ,  Jiwon Kim

    IPC: H01L27/11556 ,  H01L27/11582 ,  H01L23/528 ,  G11C5/06 ,  G11C5/02

    Abstract: Disclosed is a three-dimensional semiconductor memory device including a substrate including a cell array region and a connection region, a stack including first and second stacks sequentially stacked on the substrate, the stack having a staircase structure on the connection region, each of the first and second stacks including conductive patterns vertically stacked on the substrate, and contact plugs disposed on the connection region and respectively coupled to the conductive patterns. A bottom surface of each contact plug is located between top and bottom surfaces of a corresponding conductive pattern. In each stack, a recess depth of each contact plug varies monotonically in a stacking direction of the conductive patterns, when measured from a top surface of a corresponding conductive pattern. The contact plugs coupled to an uppermost conductive pattern of the first stack and a lowermost conductive pattern of the second stack have discrete recess depths.

    Three-dimensional semiconductor memory device
    8.
    发明授权
    Three-dimensional semiconductor memory device 有权

    公开(公告)号：US11641738B2

    公开(公告)日：2023-05-02

    申请号：US17021416

    申请日：2020-09-15

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Woosung Yang ,  Byungjin Lee ,  Bumkyu Kang ,  Dong-Sik Lee

    IPC: H01L27/11539 ,  H01L23/522 ,  H01L27/11519 ,  H01L27/11551 ,  H01L27/11565 ,  H01L27/11573 ,  H01L23/528 ,  H01L27/11543 ,  G11C16/08 ,  G11C7/18 ,  H01L27/11578

    Abstract: A three-dimensional semiconductor memory device including a first peripheral circuit including different decoder circuits, a first memory on the first peripheral circuit, the first memory including a first stack structure having first electrode layers stacked on one another and first inter-electrode dielectric layers therebetween, a first planarized dielectric layer covering an end of the first stack structure, and a through via that penetrates the end of the first stack structure, the through via electrically connected to one of the decoder circuits, and a second memory on the first memory and including a second stack structure having second electrode layers stacked on one another and second inter-electrode dielectric layers therebetween, a second planarized dielectric layer covering an end of the second stack structure, and a cell contact plug electrically connecting one of the second electrode layers to the through via.

    Integrated circuit device and method of fabricating the same
    9.
    发明授权
    Integrated circuit device and method of fabricating the same 有权

    公开(公告)号：US11251196B2

    公开(公告)日：2022-02-15

    申请号：US16749255

    申请日：2020-01-22

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Jaeho Ahn ,  Woosung Yang ,  Joonsung Lim ,  Sungmin Hwang

    IPC: H01L27/11582 ,  H01L27/11556 ,  H01L23/528 ,  H01L27/11526 ,  H01L23/522 ,  H01L25/065 ,  H01L23/00 ,  H01L27/11573

    Abstract: An integrated circuit device includes: a lower memory stack including a plurality of lower word lines located on a substrate, an upper memory stack located on the lower memory stack and including a plurality of upper word lines, at least one first lower interconnection layer extending in a horizontal direction at a first vertical level between the lower memory stack and the upper memory stack, and configured to be electrically connected to at least one lower word line selected from the plurality of lower word lines, a separate insulating film covering at least one first lower interconnection layer, and at least one first upper interconnection layer extending in the horizontal direction at a second vertical level higher than the upper memory stack, and configured to be electrically connected to at least one upper word line selected from the upper word lines.

    SEMICONDUCTOR DEVICE AND SEMICONDUCTOR PACKAGE INCLUDING THE SAME
    10.
    发明申请
    SEMICONDUCTOR DEVICE AND SEMICONDUCTOR PACKAGE INCLUDING THE SAME 有权

    公开(公告)号：US20240371730A1

    公开(公告)日：2024-11-07

    申请号：US18411171

    申请日：2024-01-12

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Ahreum Lee ,  Woosung Yang ,  Jimo Gu ,  Sukkang Sung

    IPC: H01L23/48 ,  H01L23/00 ,  H01L25/065 ,  H10B80/00

    Abstract: Disclosed are semiconductor devices and semiconductor packages including the same. The semiconductor package includes a package substrate, and a first chip stack and a second chip stack that are stacked on the package substrate. Each of the first and second chip stacks includes a plurality of vertically stacked semiconductor chips. Each of the semiconductor chips includes a plurality of first vertical connection structures and a plurality of second vertical connection structures. The first vertical connection structures of the semiconductor chips in the second chip stack overlap and are connected with the second vertical connection structures of the semiconductor chips in the first chip stack.

Patent Agency Ranking