公开(公告)号：US20220406814A1

公开(公告)日：2022-12-22

申请号：US17895182

申请日：2022-08-25

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： WOOSUNG YANG ,  BYUNGJIN LEE ,  BUMKYU KANG ,  JOONSUNG LIM

IPC: H01L27/11582 ,  H01L27/11565 ,  H01L27/11573 ,  H01L27/1157 ,  H01L27/11519 ,  H01L23/00 ,  H01L27/11556 ,  H01L27/11526 ,  G11C7/18 ,  H01L23/522 ,  H01L27/11524

Abstract: A memory device includes a lower structure and a plurality of upper structures stacked on the lower structure. The lower structure includes a peripheral circuit, and an upper bonding pad disposed on a top surface of the lower structure. Each of the plurality of upper structures includes a bit line, a through via, and a lower bonding pad disposed on a bottom surface of the upper structures and connected to the through via. Each of upper structures, other than an uppermost upper structure, further includes an upper bonding pad disposed on a top surface thereof and connected to the through via. The bit line includes a gap separating a first portion of the bit line from a second portion thereof in the horizontal direction, and the through via overlaps the gap of the bit line in a plan view.

公开(公告)号：US20210225867A1

公开(公告)日：2021-07-22

申请号：US17007141

申请日：2020-08-31

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： WOOSUNG YANG ,  BYUNGJIN LEE ,  BUMKYU KANG ,  JOONSUNG LIM

IPC: H01L27/11582 ,  H01L27/11565 ,  H01L27/11573 ,  H01L27/1157 ,  H01L27/11519 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/11526 ,  G11C7/18 ,  H01L23/522 ,  H01L23/00

Abstract: A memory device includes a lower structure and a plurality of upper structures stacked on the lower structure. The lower structure includes a peripheral circuit, and an upper bonding pad disposed on a top surface of the lower structure. Each of the plurality of upper structures includes a bit line, a through via, and a lower bonding pad disposed on a bottom surface of the upper structures and connected to the through via. Each of upper structures, other than an uppermost upper structure, further includes an upper bonding pad disposed on a top surface thereof and connected to the through via. The bit line includes a gap separating a first portion of the bit line from a second portion thereof in the horizontal direction, and the through via overlaps the gap of the bit line in a plan view.

公开(公告)号：US20210225870A1

公开(公告)日：2021-07-22

申请号：US17026377

申请日：2020-09-21

Applicant: Samsung Electronics Co., Ltd.

Inventor： WOOSUNG YANG ,  HOJUN SEONG ,  JOONHEE LEE ,  JOON-SUNG LIM ,  EUNTAEK JUNG

IPC: H01L27/11582 ,  H01L27/11565 ,  H01L23/522 ,  H01L27/11573 ,  H01L27/11519 ,  H01L27/11556 ,  H01L27/11539

Abstract: Disclosed is a semiconductor memory device comprising a second substrate on a first substrate and including a lower semiconductor layer and an upper semiconductor layer on the lower semiconductor layer, an electrode structure on the upper semiconductor layer and including a plurality of stacked electrodes, a vertical channel structure that penetrates the electrode structure and is connected to the second substrate, an interlayer dielectric layer that covers the electrode structure, and a cutting structure that penetrates the interlayer dielectric layer and the upper semiconductor layer. The upper semiconductor layer has a first sidewall defined by the cutting structure. The lower semiconductor layer has a second sidewall adjacent to the first sidewall. The first sidewall and the second sidewall are horizontally offset from each other.

公开(公告)号：US20240128135A1

公开(公告)日：2024-04-18

申请号：US18331975

申请日：2023-06-09

Applicant: Samsung Electronics Co., Ltd.

Inventor： GYOSOO CHOO ,  DAESEOK BYEON ,  WOOSUNG YANG

IPC: H01L21/66 ,  H01L23/00 ,  H01L23/544 ,  H01L25/065

CPC classification number: H01L22/34 ,  H01L22/14 ,  H01L23/544 ,  H01L24/08 ,  H01L25/0657 ,  H01L2224/08148 ,  H01L2225/06565 ,  H01L2924/1438 ,  H01L2924/35121

Abstract: A semiconductor device with a structure in which a plurality of chips are stacked includes: a chip area; a scribe lane at a circumference of the chip area; a dam structure that separates the chip area and the scribe lane; a detection wire that extends from the chip area to the scribe lane by passing through the dam structure; and a detection circuit in the chip area that is electrically connected to the detection wire and is configured to detect a defect in the scribe lane.

公开(公告)号：US20220223619A1

公开(公告)日：2022-07-14

申请号：US17706426

申请日：2022-03-28

Applicant: Samsung Electronics Co., Ltd.

Inventor： WOOSUNG YANG ,  DONG-SIK LEE ,  SUNG-MIN HWANG ,  JOON-SUNG LIM

IPC: H01L27/11582 ,  H01L27/11526 ,  H01L27/11556 ,  H01L23/522 ,  H01L23/528 ,  H01L21/28 ,  H01L29/66 ,  H01L27/11519 ,  H01L27/11565 ,  H01L27/11573

Abstract: A three-dimensional semiconductor memory device may include horizontal patterns disposed on a peripheral circuit structure and spaced apart from each other, memory structures provided on the horizontal patterns, respectively, each of the memory structures including a three-dimensional arrangement of memory cells. Penetrating insulating patterns and separation structures may isolate the horizontal patterns from one another. Through vias may extend through the penetrating insulating patterns to connect logic circuits of the peripheral circuit structure to the memory structure.