公开(公告)号：US20230317513A1

公开(公告)日：2023-10-05

申请号：US18332149

申请日：2023-06-09

Applicant: Samsung Electronics Co., Ltd.

Inventor： Ming HE ,  Harsono SIMKA ,  Rebecca PARK

IPC: H01L21/768 ,  H01L23/522

CPC classification number: H01L21/76813 ,  H01L21/76877 ,  H01L23/5226 ,  H01L21/76831

Abstract: A method and electronic device are provided. The electronic device includes a first dielectric layer; a metal patterned in the first dielectric layer; a second dielectric layer deposited on the first dielectric layer; and a metal via deposited in a channel in the second dielectric layer, the metal via being in contact with the patterned metal in the first dielectric layer. The channel is formed by removing at least a portion of a nanowall formed on the metal in the first dielectric layer.

公开(公告)号：US20250024689A1

公开(公告)日：2025-01-16

申请号：US18767862

申请日：2024-07-09

Applicant: SAMSUNG ELECTRONICS CO., LTD. ,  The Board of Trustees of the Leland Stanford Junior University

Inventor： William San-Hsi HWANG ,  Shan Xiang WANG ,  Fen Xue ,  Wilman TSAI ,  Harsono SIMKA

IPC: H10B61/00 ,  G01R33/07 ,  G01R33/09 ,  H10N50/10 ,  H10N50/20

Abstract: An magnetoresistive random access memory (MRAM) device includes a magnetic tunnel junction, and a spin-orbit torque material. Based on a current applied to the spin-orbit torque material, the spin-orbit torque material generates spin polarization along one or multiple axes.

公开(公告)号：US20220301924A1

公开(公告)日：2022-09-22

申请号：US17326973

申请日：2021-05-21

Applicant: Samsung Electronics Co., Ltd.

Inventor： Ming HE ,  Harsono SIMKA ,  Rebecca PARK

IPC: H01L21/768 ,  H01L23/522

Abstract: A method and electronic device are provided. The method includes patterning a metal in a first dielectric layer, depositing a first metal layer over the patterned metal, forming a nanowall under the first metal layer such that the nanowall is in contact with the patterned metal in the first dielectric layer, depositing a second dielectric layer on the first dielectric layer, removing at least a portion of the nanowall, thereby forming a channel in the second dielectric layer, and depositing a metal via in the channel such that the metal via is in contact with the patterned metal in the first dielectric layer.

公开(公告)号：US20240429307A1

公开(公告)日：2024-12-26

申请号：US18745976

申请日：2024-06-17

Applicant: Samsung Electronics Co., Ltd.

Inventor： Rebecca PARK ,  Mehdi SAREMI ,  Ming HE ,  Muhammed AHOSAN UL KARIM ,  Aravindh KUMAR ,  Harsono SIMKA

IPC: H01L29/66 ,  H01L29/417 ,  H01L29/78

Abstract: Provided are systems, methods, and apparatuses for applying stress in transistors. In one or more examples, the systems, devices, and methods include depositing an epitaxial film on a surface between a first sidewall and a second sidewall of the transistor; depositing a dielectric over the epitaxial film and on the surface between the first sidewall and the second sidewall to increase stress in a silicon channel of the transistor; removing a polysilicon fin between the second sidewall and a third sidewall; and depositing a first metal between the second sidewall and the third sidewall based on removing the polysilicon fin.

公开(公告)号：US20240047456A1

公开(公告)日：2024-02-08

申请号：US17984042

申请日：2022-11-09

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Ming HE ,  Mehdi SAREMI ,  Rebecca PARK ,  Muhammed AHOSAN UL KARIM ,  Harsono SIMKA ,  Sungil PARK ,  Myungil KANG ,  Kyungho KIM ,  Doyoung CHOI ,  JaeHyun PARK

IPC: H01L27/088 ,  H01L29/417 ,  H01L29/06 ,  H01L29/423 ,  H01L29/78

CPC classification number: H01L27/088 ,  H01L29/41725 ,  H01L29/0607 ,  H01L29/42392 ,  H01L29/0673 ,  H01L29/785

Abstract: Provided is a three-dimensionally stacked field-effect transistor (3DSFET) device which includes: a 1st lower source/drain region and a 2nd lower source/drain region connected to each other through a 1st lower channel structure controlled by a 1st gate structure; and a 1st upper source/drain region and a 2nd upper source/drain regions, respectively above the 1st lower source/drain region and the 2nd lower source/drain region, and connected to each other through a 1st upper channel structure controlled by the 1st gate structure, wherein the 2nd lower source/drain region and the 2nd upper source/drain region form a PN junction therebetween.