公开(公告)号：US20240120401A1

公开(公告)日：2024-04-11

申请号：US18390246

申请日：2023-12-20

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sungil PARK ,  Jae Hyun PARK ,  Kyungho KIM ,  Cheoljin YUN ,  Daewon HA

IPC: H01L29/423 ,  H01L29/786

CPC classification number: H01L29/42392 ,  H01L29/78618 ,  H01L29/78696

Abstract: A semiconductor device includes a lower channel pattern and an upper channel pattern stacked on a substrate in a first direction perpendicular to a top surface of the substrate, lower source/drain patterns on the substrate and at a first side and a second side of the lower channel pattern, upper source/drain patterns stacked on the lower source/drain patterns and at a third side and a fourth side of the upper channel pattern, a first barrier pattern between the lower source/drain patterns and the upper source/drain patterns, and a second barrier pattern between the first barrier pattern and the upper source/drain patterns. The first barrier pattern includes a first material and the second barrier pattern includes a second material, wherein the first material and the second material are different.

公开(公告)号：US20240030287A1

公开(公告)日：2024-01-25

申请号：US18340440

申请日：2023-06-23

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Choeun LEE ,  Kyungho KIM ,  Kanghun MOON ,  Kihwan KIM ,  Yonguk JEON

IPC: H01L29/08 ,  H01L29/06 ,  H01L29/161 ,  H01L29/423 ,  H01L29/417 ,  H01L29/775 ,  H01L21/02 ,  H01L29/66

CPC classification number: H01L29/0847 ,  H01L29/0673 ,  H01L29/161 ,  H01L29/42392 ,  H01L29/41733 ,  H01L29/775 ,  H01L21/02532 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/66439

Abstract: A semiconductor device includes a plurality of channel layers on an active region on a substrate, a gate structure surrounding each of the plurality of channel layers, and a source/drain region contacting the plurality of channel layers. The source/drain region comprises a first epitaxial layer including first layers, disposed on side surfaces of the plurality of channel layers, and a second layer, disposed at a lower end of the source/drain region on the active region, and having first impurities, a second epitaxial layer on the active region, filling a space between the first layers and the second layer, having second impurities, different from the first impurities, and having a recessed upper surface, and a third epitaxial layer on the second epitaxial layer. At least a portion of the third epitaxial layer may not include the first impurities and the second impurities.

公开(公告)号：US20230395660A1

公开(公告)日：2023-12-07

申请号：US18100688

申请日：2023-01-24

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Kihwan KIM ,  Kyungho KIM ,  Kanghun MOON ,  Choeun LEE ,  Yonguk JEON

IPC: H01L29/06 ,  H01L29/08 ,  H01L29/78 ,  H01L29/786 ,  H01L29/775

CPC classification number: H01L29/0673 ,  H01L29/0847 ,  H01L29/7851 ,  H01L29/78696 ,  H01L29/775

Abstract: A semiconductor device, including a fin active region; a device isolation layer covering two sidewalls of the fin active region on the substrate; a gate structure; a nano-sheet structure including a plurality of nano-sheets; and source/drain regions disposed on the fin active region and adjacent to the gate structure, wherein each source/drain region of the source/drain regions includes a buffer layer, an inner impurity layer, and a central impurity layer which are sequentially stacked, wherein the buffer layer fills a first indentation between two vertically-adjacent nano-sheets and a second indentation between the top surface of the fin active region and a nano-sheet, and wherein the plurality of nano-sheets contact side surfaces of the inner impurity layer.

公开(公告)号：US20160315625A1

公开(公告)日：2016-10-27

申请号：US15179202

申请日：2016-06-10

Applicant: Samsung Electronics Co., Ltd.

Inventor： Junhan BAE ,  Kee-Won KWON ,  Kyungho KIM ,  Jung Hoon CHUN ,  Youngsoo SOHN ,  Seok KIM

IPC: H03L7/089 ,  H03L7/099

CPC classification number: H03L7/0891 ,  H03D13/004 ,  H03L7/081 ,  H03L7/085 ,  H03L7/087 ,  H03L7/0995 ,  H03L7/104 ,  H03L7/107 ,  H03L7/1072

Abstract: A phase-rotating phase locked loop (PLL) may include first and second loops that share a loop filter and a voltage controlled oscillator in order to perform the operation of a phase-rotating PLL, the first and second loops configured to activate in response to an enable signal. The PLL may further include a phase frequency detection controller configured to provide the enable signal to the first and second loops in response to a transition of a coarse signal that may be applied as a digital code.

Abstract translation: 相位旋转锁相环（PLL）可以包括共享环路滤波器和压控振荡器的第一和第二回路，以便执行相位旋转PLL的操作，第一和第二回路被配置为响应于 一个使能信号。 PLL可以进一步包括相位频率检测控制器，其被配置为响应于作为数字代码应用的粗略信号的转变，向第一和第二环路提供使能信号。

公开(公告)号：US20190239769A1

公开(公告)日：2019-08-08

申请号：US16270736

申请日：2019-02-08

Applicant: Samsung Electronics Co., Ltd.

Inventor： Minhyoung LEE ,  Kyungho KIM ,  Doyoon KIM ,  Moorim KIM ,  Sangjoon PARK ,  Seongdae YANG ,  Hayoul JUNG ,  Woochul LEE ,  Byunghun CHO

IPC: A61B5/0408 ,  A61B5/0432 ,  A61B5/00

CPC classification number: A61B5/04085 ,  A61B5/0022 ,  A61B5/0432 ,  A61B5/6833 ,  A61B2560/0214 ,  H01F7/02

Abstract: An electronic device and method are disclosed herein. The electronic device includes a housing, electrodes disposed on a face of the housing, and a processor which implements the method. The method includes in response to an electrocardiogram request, detecting a first signal using a first electrode and a fourth electrode from among the plurality of electrodes, detecting a second signal using a second electrode and the fourth electrode, detecting a third signal using a third electrode and the fourth electrode, and storing in the memory the first signal and the second signal as a first biological signal, the second signal and the third signal as a second biological signal and the third signal and the first signal as a third biological signal in association with the requested electrocardiogram measurement.

公开(公告)号：US20220416045A1

公开(公告)日：2022-12-29

申请号：US17583314

申请日：2022-01-25

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sungil PARK ,  Jae Hyun PARK ,  Kyungho KIM ,  Cheoljin YUN ,  Daewon HA

IPC: H01L29/423 ,  H01L29/786

Abstract: A semiconductor device includes a lower channel pattern and an upper channel pattern stacked on a substrate in a first direction perpendicular to a top surface of the substrate, lower source/drain patterns on the substrate and at a first side and a second side of the lower channel pattern, upper source/drain patterns stacked on the lower source/drain patterns and at a third side and a fourth side of the upper channel pattern, a first barrier pattern between the lower source/drain patterns and the upper source/drain patterns, and a second barrier pattern between the first barrier pattern and the upper source/drain patterns. the first barrier pattern includes a first material and the second barrier pattern includes a second material, wherein the first material and the second material are different.

公开(公告)号：US20240105724A1

公开(公告)日：2024-03-28

申请号：US18196741

申请日：2023-05-12

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： DONGHOON HWANG ,  MYUNGIL KANG ,  MINCHAN GWAK ,  Kyungho KIM ,  Kyung Hee CHO ,  DOYOUNG CHOI

IPC: H01L27/092 ,  H01L21/822 ,  H01L21/8238 ,  H01L29/06 ,  H01L29/417 ,  H01L29/423 ,  H01L29/66 ,  H01L29/775

CPC classification number: H01L27/0922 ,  H01L21/8221 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823871 ,  H01L29/0673 ,  H01L29/41733 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/66545 ,  H01L29/775

Abstract: A three-dimensional semiconductor device includes a first active region on a substrate, the first active region including a lower channel pattern and a lower source/drain pattern connected to the lower channel pattern, a second active region stacked on the first active region, the second active region including an upper channel pattern and an upper source/drain pattern connected to the upper channel pattern, a gate electrode on the lower channel pattern and the upper channel pattern, a lower contact electrically connected to the lower source/drain pattern, the lower contact having a bar shape extending on the lower source/drain pattern in a first direction, a first active contact coupled to the lower contact, and a second active contact coupled to the upper source/drain pattern. A first width of the lower source/drain pattern in a second direction is larger than a second width of the lower contact in the second direction.

公开(公告)号：US20240047456A1

公开(公告)日：2024-02-08

申请号：US17984042

申请日：2022-11-09

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Ming HE ,  Mehdi SAREMI ,  Rebecca PARK ,  Muhammed AHOSAN UL KARIM ,  Harsono SIMKA ,  Sungil PARK ,  Myungil KANG ,  Kyungho KIM ,  Doyoung CHOI ,  JaeHyun PARK

IPC: H01L27/088 ,  H01L29/417 ,  H01L29/06 ,  H01L29/423 ,  H01L29/78

CPC classification number: H01L27/088 ,  H01L29/41725 ,  H01L29/0607 ,  H01L29/42392 ,  H01L29/0673 ,  H01L29/785

Abstract: Provided is a three-dimensionally stacked field-effect transistor (3DSFET) device which includes: a 1st lower source/drain region and a 2nd lower source/drain region connected to each other through a 1st lower channel structure controlled by a 1st gate structure; and a 1st upper source/drain region and a 2nd upper source/drain regions, respectively above the 1st lower source/drain region and the 2nd lower source/drain region, and connected to each other through a 1st upper channel structure controlled by the 1st gate structure, wherein the 2nd lower source/drain region and the 2nd upper source/drain region form a PN junction therebetween.