公开(公告)号：US20240233857A1

公开(公告)日：2024-07-11

申请号：US18395010

申请日：2023-12-22

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Kuihan Ko ,  Sang-Won Park ,  Won-Taeck Jung ,  Heewon Son ,  Bongsoon Lim

IPC: G11C29/56

CPC classification number: G11C29/56004 ,  G11C29/56012 ,  G11C29/56016 ,  G11C2029/5602

Abstract: A memory device includes a memory cell array, a reference generating circuit, a row decoding circuit that is connected to the memory cell array through word lines, a page buffer circuit that is connected to the memory cell array through bit lines, a data input/output circuit that is connected to the page buffer circuit through a data line, a buffer circuit, a control logic circuit that performs logic sequences, based on the internal clock signal and the internal power, and a test mode circuit. When the memory device enters a test mode, the test mode circuit disables a part of components of the reference generating circuit. In the test mode, the control logic circuit performs the logic sequences by using an external clock signal provided from an external device.

公开(公告)号：US20250014670A1

公开(公告)日：2025-01-09

申请号：US18399872

申请日：2023-12-29

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sang-Won Park ,  Kuihan Ko ,  Heewon Son

IPC: G11C29/52 ,  G11C16/08 ,  G11C16/16

Abstract: A non-volatile integrated circuit memory device includes a first memory block having first and second memory sub-blocks therein, and a second memory block having third and fourth memory sub-blocks therein. A sub-block manager is also provided, which is configured to: (i) determine whether the second memory sub-block is a reclaim sub-block when the first memory sub-block has an uncorrectable error (UECC) therein, and (ii) reclaim the first and second memory sub-blocks to the third and fourth memory sub-blocks, respectively, in response to determining that the second memory sub-block is a reclaim sub-block.