公开(公告)号：US08988950B2

公开(公告)日：2015-03-24

申请号：US14056370

申请日：2013-10-17

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jong-Min Oh ,  Ho-Yong Song ,  Seong-Jin Jang

IPC: G11C19/00 ,  G11C11/4093 ,  G11C7/10 ,  G11C8/04 ,  G11C29/04

CPC classification number: G11C29/86 ,  G11C7/1036 ,  G11C7/1051 ,  G11C8/04 ,  G11C11/4093 ,  G11C16/20 ,  G11C17/16 ,  G11C2029/0407 ,  G11C2207/107

Abstract: A data loading circuit comprises a non-volatile memory configured to store non-volatile data and output a serial data signal based on the stored non-volatile data in response to a power-up operation, a deserializer configured to receive the serial data signal and output multiple data bits at intervals of a unit period based on the received serial data signal, a load controller configured to generate multiple loading selection signals that are sequentially activated one-by-one at each interval of the unit period, and a loading memory unit configured to sequentially store the data bits at each interval of the unit period in response to the loading selection signals.

Abstract translation: 数据加载电路包括被配置为存储非易失性数据并响应于上电操作基于所存储的非易失性数据输出串行数据信号的非易失性存储器，被配置为接收串行数据信号的解串器和 基于所接收的串行数据信号以单位周期的间隔输出多个数据位;负载控制器，被配置为生成在所述单位周期的每个间隔逐个依次激活的多个加载选择信号;以及加载存储器单元 被配置为响应于所述加载选择信号在所述单位周期的每个间隔顺序地存储所述数据位。