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1.发明授权Memory device, method of operating the same, and electronic device having the memory device 有权存储装置，其操作方法和具有存储装置的电子装置公开(公告)号：US08897055B2
公开(公告)日：2014-11-25
申请号：US13771633
申请日：2013-02-20
Applicant: Samsung Electronics Co., Ltd.
Inventor： Je-Min Ryu , Gil-Su Kim , Jong-Min Oh , Sung-Min Seo , Ho-Young Song , Yong-Ho Cho
CPC classification number: G11C17/16 , G11C7/1045 , G11C17/18 , G11C29/802
Abstract: A memory device includes a memory cell array and a fuse device. The fuse device includes a fuse cell array and a fuse control circuit. The fuse cell array includes a first fuse cell sub-array which stores first data associated with operation of the fuse control circuit, and a second fuse cell sub-array which stores second data associated with operation of the memory device. The fuse control circuit is electrically coupled to the first and second fuse cell sub-arrays, and is configured to read the first and second data from the first and second fuse cell sub-arrays, respectively.
Abstract translation: 存储器件包括存储单元阵列和熔丝器件。 保险丝装置包括熔丝单元阵列和熔丝控制电路。 熔丝单元阵列包括存储与熔丝控制电路的操作相关联的第一数据的第一熔丝单元子阵列和存储与存储器件的操作相关联的第二数据的第二熔丝单元子阵列。 熔丝控制电路电耦合到第一和第二熔丝单元子阵列，并且被配置为分别从第一和第二熔丝单元子阵列读取第一和第二数据。
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公开(公告)号：US10446216B2
公开(公告)日：2019-10-15
申请号：US15134637
申请日：2016-04-21
Applicant: Samsung Electronics Co., Ltd.
Inventor： Jong-Min Oh , Ho-Young Song , Do-Yeon Kim
IPC: G11C11/406 , G11C11/4072 , G11C11/408 , G11C11/4076
Abstract: Embedded refresh controllers included in memory devices and memory devices including the embedded refresh controllers are provided. The embedded refresh controllers may include a refresh counter and an address generator. The refresh counter may generate a counter refresh address signal in response to a counter refresh signal such that the counter refresh address signal may represent a sequentially changing address. The address generator may store information with respect to a hammer address that is accessed intensively and may generates a hammer refresh address signal in response to a hammer refresh signal such that the hammer refresh address signal may represent an address of a row that is physically adjacent to a row of the hammer address. Loss of cell data may be reduced and performance of the memory device may be enhanced by detecting the intensively-accessed hammer address and performing the refresh operation based on the detected hammer address efficiently.
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公开(公告)号：US09384861B2
公开(公告)日：2016-07-05
申请号：US14623133
申请日：2015-02-16
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Jong-Min Oh , Ho-Young Song , Seong-Jin Jang
CPC classification number: G11C29/86 , G11C7/1036 , G11C7/1051 , G11C8/04 , G11C11/4093 , G11C16/20 , G11C17/16 , G11C2029/0407 , G11C2207/107
Abstract: A data loading circuit comprises a non-volatile memory configured to store non-volatile data and output a serial data signal based on the stored non-volatile data in response to a power-up operation, a deserializer configured to receive the serial data signal and output multiple data bits at intervals of a unit period based on the received serial data signal, a load controller configured to generate multiple loading selection signals that are sequentially activated one-by-one at each interval of the unit period, and a loading memory unit configured to sequentially store the data bits at each interval of the unit period in response to the loading selection signals.
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公开(公告)号：US09293218B2
公开(公告)日：2016-03-22
申请号：US14049399
申请日：2013-10-09
Applicant: Samsung Electronics Co., Ltd.
Inventor： Je-Min Yu , Sung-Min Seo , Ho-Young Song , Gil-Su Kim , Jong-Min Oh
CPC classification number: G11C17/08 , G11C16/04 , G11C16/0483 , G11C17/16 , G11C17/18 , G11C29/785
Abstract: Provided is a semiconductor memory device. The semiconductor includes a One Time Programmable (OTP) cell array, a converging circuit and a sense amplifier circuit. The OTP cell array includes a plurality of OTP cells connected to a plurality of bit lines, each bit line extending in a first direction. The converging includes a common node contacting a first bit line and a second bit line. The sense amplifier circuit includes a sense amplifier connected to the common node, the sense amplifier configured to amplify a signal of the common node.
Abstract translation: 提供了一种半导体存储器件。 该半导体包括一个可编程（OTP）单元阵列，一个会聚电路和一个读出放大器电路。 OTP单元阵列包括连接到多个位线的多个OTP单元，每个位线沿第一方向延伸。 收敛包括接触第一位线和第二位线的公共节点。 感测放大器电路包括连接到公共节点的读出放大器，该读出放大器配置成放大公共节点的信号。
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Patent Agency Ranking
5.发明授权Anti-fuse circuit in which anti-fuse cell data is monitored, and semiconductor device including the same 有权防熔丝电池数据被监视的反熔丝电路，以及包括其的半导体器件公开(公告)号：US09036441B2
公开(公告)日：2015-05-19
申请号：US13793457
申请日：2013-03-11
Applicant: Samsung Electronics Co., Ltd.
Inventor： Jong-Min Oh , Ho-Young Song , Seong-Jin Jang
Abstract: An anti-fuse circuit in which anti-fuse program data may be monitored outside of the anti-fuse circuit and a semiconductor device including the anti-fuse circuit are disclosed. The anti-fuse circuit includes an anti-fuse array, a data storage circuit, and a first selecting circuit. The anti-fuse array includes one or more anti-fuse blocks including a first anti-fuse block having a plurality of anti-fuse cells and the anti-fuse array is configured to store anti-fuse program data. The data storage circuit is configured to receive and store the anti-fuse program data from the anti-fuse array through one or more data buses. The first selecting circuit is configured to output anti-fuse program data of a selected anti-fuse block of the one or more anti-fuse blocks in response to a first selection signal.
Abstract translation: 公开了一种其中可以在反熔丝电路外面监视反熔丝程序数据的反熔丝电路和包括反熔丝电路的半导体器件。 反熔丝电路包括反熔丝阵列，数据存储电路和第一选择电路。 反熔丝阵列包括一个或多个抗熔丝块，其包括具有多个反熔丝单元的第一反熔丝块，并且反熔丝阵列被配置为存储反熔丝程序数据。 数据存储电路被配置为通过一个或多个数据总线接收并存储来自反熔丝阵列的反熔丝程序数据。 第一选择电路被配置为响应于第一选择信号输出所述一个或多个反熔丝块的所选反熔丝块的反熔丝程序数据。
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公开(公告)号：US09972377B2
公开(公告)日：2018-05-15
申请号：US15262183
申请日：2016-09-12
Applicant: Samsung Electronics Co., Ltd.
Inventor： Jong-Min Oh , Ho-Young Song
IPC: G11C11/406 , G11C11/408 , G11C11/4076
CPC classification number: G11C11/40615 , G11C11/406
Abstract: A refresh controller of a memory device may include a timing controller, a refresh counter and an address generator. The timing controller generates a counter refresh signal in response to receiving a refresh command provided from an external device, and generates a hammer refresh signal that is activated periodically. The refresh counter generates a counter refresh address signal in response to the counter refresh signal, such that the counter refresh address signal represents a row address, the refresh counter being configured sequentially change the counter refresh address signal. The address generator generates a hammer refresh address signal in response to the hammer refresh signal, the hammer refresh address signal representing an address of a row of the memory device that is physically adjacent to a row of the memory device corresponding to a hammer address that is accessed intensively.
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7.发明授权Fuse data reading circuit having multiple reading modes and related devices, systems and methods 有权具有多种读取模式和相关设备，系统和方法的保险丝数据读取电路公开(公告)号：US09343175B2
公开(公告)日：2016-05-17
申请号：US13835319
申请日：2013-03-15
Applicant: Samsung Electronics Co., Ltd.
Inventor： Gil-Su Kim , Jong-Min Oh , Sung-Min Seo , Je-Min Ryu , Seong-Jin Jang
CPC classification number: G11C17/18 , G11C7/14 , G11C17/16 , G11C29/789
Abstract: A fuse data reading circuit is configured to read fuse data in multi-reading modes. The fuse data may be stored in a fuse array that includes a plurality of fuse cells configured to store fuse data. The fuse data reading circuit may include a sensing unit configured to sense the fuse data stored in the fuse cells of the fuse array, and a controller configured to control an operation of reading the fuse data stored in the fuse cells. The controller sets different sensing conditions for sensing the fuse data according to an operation period during the fuse data reading operation to read the fuse data. Methods include operations and use of the fuse data reading circuit.
Abstract translation: 熔丝数据读取电路被配置为以多读取模式读取熔丝数据。 熔丝数据可以存储在包括被配置为存储熔丝数据的多个熔丝单元的熔丝阵列中。 熔丝数据读取电路可以包括感测单元，其被配置为感测存储在熔丝阵列的熔丝单元中的熔丝数据，以及控制器，被配置为控制读取存储在熔丝单元中的熔丝数据的操作。 控制器根据熔丝数据读取操作期间的操作周期设置感测熔丝数据的不同感测条件以读取熔丝数据。 方法包括操作和使用熔丝数据读取电路。
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8.发明授权公开(公告)号：US08988950B2
公开(公告)日：2015-03-24
申请号：US14056370
申请日：2013-10-17
Applicant: Samsung Electronics Co., Ltd.
Inventor： Jong-Min Oh , Ho-Yong Song , Seong-Jin Jang
IPC: G11C19/00 , G11C11/4093 , G11C7/10 , G11C8/04 , G11C29/04
CPC classification number: G11C29/86 , G11C7/1036 , G11C7/1051 , G11C8/04 , G11C11/4093 , G11C16/20 , G11C17/16 , G11C2029/0407 , G11C2207/107
Abstract: A data loading circuit comprises a non-volatile memory configured to store non-volatile data and output a serial data signal based on the stored non-volatile data in response to a power-up operation, a deserializer configured to receive the serial data signal and output multiple data bits at intervals of a unit period based on the received serial data signal, a load controller configured to generate multiple loading selection signals that are sequentially activated one-by-one at each interval of the unit period, and a loading memory unit configured to sequentially store the data bits at each interval of the unit period in response to the loading selection signals.
Abstract translation: 数据加载电路包括被配置为存储非易失性数据并响应于上电操作基于所存储的非易失性数据输出串行数据信号的非易失性存储器，被配置为接收串行数据信号的解串器和 基于所接收的串行数据信号以单位周期的间隔输出多个数据位;负载控制器，被配置为生成在所述单位周期的每个间隔逐个依次激活的多个加载选择信号;以及加载存储器单元 被配置为响应于所述加载选择信号在所述单位周期的每个间隔顺序地存储所述数据位。
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9.发明申请MEMORY DEVICE, METHOD OF OPERATING THE SAME, AND ELECTRONIC DEVICE HAVING THE MEMORY DEVICE 有权存储器件，其操作方法和具有存储器件的电子器件公开(公告)号：US20130322149A1
公开(公告)日：2013-12-05
申请号：US13771633
申请日：2013-02-20
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Je-Min Ryu , Gil-Su Kim , Jong-Min Oh , Sung-Min Seo , Ho-Young Song , Yong-Ho Cho
CPC classification number: G11C17/16 , G11C7/1045 , G11C17/18 , G11C29/802
Abstract: A memory device includes a memory cell array and a fuse device. The fuse device includes a fuse cell array and a fuse control circuit. The fuse cell array includes a first fuse cell sub-array which stores first data associated with operation of the fuse control circuit, and a second fuse cell sub-array which stores second data associated with operation of the memory device. The fuse control circuit is electrically coupled to the first and second fuse cell sub-arrays, and is configured to read the first and second data from the first and second fuse cell sub-arrays, respectively.
Abstract translation: 存储器件包括存储单元阵列和熔丝器件。 保险丝装置包括熔丝单元阵列和熔丝控制电路。 熔丝单元阵列包括存储与熔丝控制电路的操作相关联的第一数据的第一熔丝单元子阵列和存储与存储器件的操作相关联的第二数据的第二熔丝单元子阵列。 熔丝控制电路电耦合到第一和第二熔丝单元子阵列，并且被配置为分别从第一和第二熔丝单元子阵列读取第一和第二数据。
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