公开(公告)号：US11894090B2

公开(公告)日：2024-02-06

申请号：US18117583

申请日：2023-03-06

申请人： Micron Technology, Inc.

发明人： Zhenlei Shen ,  Tingjun Xie ,  Zhenming Zhou

IPC分类号： G11C29/00 ,  G11C29/42 ,  G06F11/10 ,  G06F3/06 ,  G11C13/00 ,  G11C29/04

CPC分类号： G11C29/42 ,  G06F3/0619 ,  G06F3/0659 ,  G06F3/0679 ,  G06F11/1068 ,  G11C13/004 ,  G11C13/0069 ,  G11C2029/0407

摘要： A system includes a memory device having groups of managed units and a processing device coupled to the memory device. The processing device, during power on of the memory device, causes a read operation to be performed at a subset of a group of managed units and determines a bit error rate related to data read from the subset of the group of managed units. The bit error rate is a directional bit error rate resulting from an erroneously determined state compared to a programmed state that transitions between two opposing states. In response to the bit error rate satisfying a threshold criterion, the processing device causes a rewrite of the data stored at the group of managed units.

公开(公告)号：US20230333949A1

公开(公告)日：2023-10-19

申请号：US18338680

申请日：2023-06-21

申请人： Taiwan Semiconductor Manufacturing Company Limited

发明人： Shih-Lien Linus LU

IPC分类号： G06F11/22 ,  G06F11/07 ,  G06F11/30 ,  G06F12/02

CPC分类号： G06F11/2284 ,  G06F11/073 ,  G06F11/076 ,  G06F11/3037 ,  G06F12/0246 ,  G11C2029/0407

摘要： Disclosed herein are related to an age detector for determining an age of a memory block, and a method of operation of the age detector. In one configuration, a memory system includes a memory block and an age detector coupled to the memory block. In one aspect, the memory block generates a first set of data in response to a first power on, and generates a second set of data in response to a second power on. In one configuration, the age detector includes a storage block to store the first set of data from the memory block, and inconsistency detector to compare the first set of data and the second set of data. In one configuration, the age detector includes a controller to determine an age of the memory block, based on the comparison.

公开(公告)号：US11762788B2

公开(公告)日：2023-09-19

申请号：US17114478

申请日：2020-12-07

申请人： Netlist, Inc.

发明人： Hyun Lee ,  Jayesh R. Bhakta

IPC分类号： G06F3/00 ,  G06F12/00 ,  G06F13/00 ,  G06F13/16 ,  G06F1/10 ,  G06F3/06 ,  G06F13/28 ,  G06F13/40 ,  G11C5/04 ,  G11C7/10 ,  G11C8/18 ,  G11C16/00 ,  G11C29/02 ,  G11C7/20 ,  G11C8/12 ,  G11C29/04

CPC分类号： G06F13/1673 ,  G06F1/10 ,  G06F3/0613 ,  G06F3/0647 ,  G06F3/0656 ,  G06F3/0659 ,  G06F3/0683 ,  G06F13/1642 ,  G06F13/28 ,  G06F13/4027 ,  G11C5/04 ,  G11C7/1006 ,  G11C7/1066 ,  G11C7/1093 ,  G11C8/18 ,  G11C16/00 ,  G11C29/023 ,  G11C29/028 ,  H05K999/99 ,  G11C7/109 ,  G11C7/20 ,  G11C8/12 ,  G11C2029/0407

摘要： A memory module is operable in a memory system with a memory controller. The memory module comprises memory devices, a module control circuit, and a plurality of buffer circuits coupled between respective sets of data signal lines in a data bus and respective sets of the memory devices. Each respective buffer circuit is mounted on the module board and coupled between a respective set of data signal lines and a respective set of memory devices. Each respective buffer circuit is configured to receive the module control signals and the module clock signal, and to buffer a respective set of data signals in response to the module control signals and the module clock signal. Each respective buffer circuit includes a delay circuit configured to delay the respective set of data signals by an amount determined based on at least one of the module control signals.

公开(公告)号：US11720458B2

公开(公告)日：2023-08-08

申请号：US17715421

申请日：2022-04-07

申请人： Taiwan Semiconductor Manufacturing Company Limited

发明人： Shih-Lien Linus Lu

IPC分类号： G06F12/00 ,  G06F11/22 ,  G06F11/07 ,  G06F11/30 ,  G06F12/02 ,  G11C29/04

CPC分类号： G06F11/2284 ,  G06F11/073 ,  G06F11/076 ,  G06F11/3037 ,  G06F12/0246 ,  G11C2029/0407

摘要： Disclosed herein are related to an age detector for determining an age of a memory block, and a method of operation of the age detector. In one configuration, a memory system includes a memory block and an age detector coupled to the memory block. In one aspect, the memory block generates a first set of data in response to a first power on, and generates a second set of data in response to a second power on. In one configuration, the age detector includes a storage block to store the first set of data from the memory block, and inconsistency detector to compare the first set of data and the second set of data. In one configuration, the age detector includes a controller to determine an age of the memory block, based on the comparison.

公开(公告)号：US20180239721A1

公开(公告)日：2018-08-23

申请号：US15959354

申请日：2018-04-23

申请人： Toshiba Memory Corporation

发明人： Yoshikazu TAKEYAMA ,  Masaru KOYANAGI ,  Akio SUGAHARA

IPC分类号： G06F13/16 ,  G11C16/08 ,  G06F13/36 ,  G06F13/40

CPC分类号： G06F13/1668 ,  G06F13/36 ,  G06F13/4068 ,  G11C7/1084 ,  G11C8/12 ,  G11C14/0018 ,  G11C16/00 ,  G11C16/0483 ,  G11C16/08 ,  G11C16/10 ,  G11C16/26 ,  G11C29/022 ,  G11C29/028 ,  G11C2029/0407 ,  G11C2029/0409

摘要： According to one embodiment, a semiconductor storage device includes a plurality of semiconductor chips and a control unit. The plurality of semiconductor chips is configured to connect to a signal transmission path and is controlled individually by individual chip enable signals. The plurality of semiconductor chips each includes a termination circuit connected to the signal transmission path. When one of the semiconductor chips is selected to input or output data, the control unit activates the termination circuit provided in the semiconductor chip that is not selected based on a first instruction signal and the chip enable signal.

公开(公告)号：US20180091003A1

公开(公告)日：2018-03-29

申请号：US15717817

申请日：2017-09-27

申请人： LAPIS SEMICONDUCTOR CO., LTD.

发明人： HIROJI AKAHORI ,  TAKASHI TAYA

IPC分类号： H02J50/80 ,  H02J50/10 ,  G11C16/34

CPC分类号： H02J50/80 ,  G11C5/142 ,  G11C16/10 ,  G11C16/102 ,  G11C16/225 ,  G11C16/30 ,  G11C16/3459 ,  G11C17/16 ,  G11C17/18 ,  G11C29/027 ,  G11C2029/0407 ,  G11C2029/4402 ,  H02J50/10

摘要： The present disclosure provides a wireless power receiver including: a power receiver configured to receive electrical power that is wirelessly transmitted from a wireless power transmitter; a power reception-side communication section configured to wirelessly communicate with the wireless power transmitter; a storage section to which data received by the power reception-side communication section is written by using the electrical power received by the power transmitter; and a monitoring section configured to monitor the electrical power or a voltage that corresponds to the electrical power supplied to the storage section in a case in which the data is being written to the storage section, the monitoring section transmits write information, which indicates whether or not the data was correctly written to the storage section based on a monitoring result, from the power reception-side communication section to the wireless power transmitter information.

公开(公告)号：US20180090225A1

公开(公告)日：2018-03-29

申请号：US15658734

申请日：2017-07-25

申请人： Renesas Electronics Corporation

发明人： Yoichi MAEDA ,  Hideshi MAENO ,  Jun MATSUSHIMA

IPC分类号： G11C29/52 ,  G06F11/27

CPC分类号： G11C29/52 ,  G06F11/27 ,  G11C29/36 ,  G11C29/38 ,  G11C29/40 ,  G11C29/44 ,  G11C2029/0401 ,  G11C2029/0407 ,  G11C2029/0409

摘要： There is to provide a semiconductor device capable of realizing a start time diagnosis on a non-volatile memory without any external device and any non-volatile memory out of a diagnosis target. The non-volatile memory includes an address space formed by addresses continuously read and a reservation address formed by a single or a plurality of addresses, read after the address space. A previously calculated value fixed data is stored in the reservation address. When all the data stored in the address space and the value fixed data are compressed using a predetermined initial value according to a predetermined compression algorithm, the value fixed data is the data for converging the compression value to a predetermined fixed value (for example, 0).

公开(公告)号：US09922724B2

公开(公告)日：2018-03-20

申请号：US15713936

申请日：2017-09-25

申请人： Samsung Electronics Co., Ltd.

发明人： Tae-Hyung Kim ,  Huichong Shin ,  Seokil Kim ,  Young Yun ,  Jonghyoung Lim ,  Youkeun Han

IPC分类号： G11C7/10 ,  G11C29/34 ,  G06F3/06 ,  G06F12/1009 ,  G11C11/4093 ,  G11C11/4076 ,  G11C5/04

CPC分类号： G11C29/34 ,  G06F3/0613 ,  G06F3/0647 ,  G06F3/0656 ,  G06F3/0688 ,  G06F12/0868 ,  G06F12/1009 ,  G06F2212/1016 ,  G06F2212/1024 ,  G11C5/04 ,  G11C7/1045 ,  G11C7/109 ,  G11C11/4076 ,  G11C11/4093 ,  G11C29/06 ,  G11C29/26 ,  G11C2029/0407

摘要： A method of operating a memory module including a plurality of semiconductor memory devices organized into a multi-rank memory on a DIMM and a memory buffer included on the DIMM, operatively coupled to the multi-rank memory, can be provided by mapping an access to the DIMM from a memory controller to semiconductor memory devices included in more than one rank within the multi-rank memory based on a mode register set signal and selectively linking rank control signals during a parallel bit test operation to the more than one rank within the multi-rank memory plurality of semiconductor memory devices.

公开(公告)号：US20180005663A1

公开(公告)日：2018-01-04

申请号：US15197588

申请日：2016-06-29

申请人： QUALCOMM Incorporated

发明人： Praveen Raghuraman ,  Nikhil Sudhakaran

IPC分类号： G11B20/18

CPC分类号： G11C29/00 ,  G11C29/12015 ,  G11C29/36 ,  G11C2029/0407 ,  G11C2029/3602

摘要： A method and apparatus for dynamic memory mode testing is provided. The method begins when an electronic device is reset before testing begins. A BIST mode is selected and then input to a BIST apparatus. The BIST mode is then performed and test results recorded. An additional BIST mode is then selected and testing using the additional BIST mode begins immediately. The apparatus includes a clock divider, a BIST controller in communication with the clock divider; a dynamic memory test module in communication with the clock divider, BIST controller and memory; and a low voltage test access port in communication with the BIST controller for receiving test output data from the BIST controller. The dynamic memory test module comprises: at least two AND gates in communication with at least three multiplexers.

公开(公告)号：US20180004599A1

公开(公告)日：2018-01-04

申请号：US15621757

申请日：2017-06-13

申请人： Nantero, Inc.

发明人： Sheyang NING

IPC分类号： G06F11/10 ,  G11C29/52 ,  G11C13/00

CPC分类号： G06F11/1068 ,  G06F11/1048 ,  G11C13/003 ,  G11C13/004 ,  G11C13/0069 ,  G11C29/44 ,  G11C29/52 ,  G11C2013/0083 ,  G11C2029/0407 ,  G11C2029/0411 ,  G11C2213/71 ,  G11C2213/79 ,  G11C2213/82

摘要： Error correction methods for arrays of resistive change elements are disclosed. An array of resistive change elements is organized into a plurality of subsections. Each subsection includes at least one flag bit and a plurality of data bits. At the start of a write operation, all bits in a subsection are initialized. If any data bits fail to initialize, the pattern of errors is compared to the input data pattern. The flag cells are then activated to indicate the appropriate encoding pattern to apply to the input data to match the errors. The input data is then encoded according to this encoding pattern before being written to the array. A second error correction algorithm can be used to correct remaining errors. During a read operation, the encoding pattern indicated by the flag bits is used to decode the read data and retrieve the original input data.