公开(公告)号：US20210104291A1

公开(公告)日：2021-04-08

申请号：US16855373

申请日：2020-04-22

Applicant: Samsung Electronics Co., Ltd.

Inventor： Byoungsul KIM ,  Hokyong LEE ,  Dongjun KIM ,  Byungmin CHOI ,  Kideok HAN

IPC: G11C29/42 ,  G11C29/44 ,  G11C29/00 ,  G11C29/14 ,  G11C11/4091 ,  G11C11/4094 ,  G11C11/408

Abstract: A memory system including a first central processing unit, a first memory module connected to the first central processing unit by a first channel, a second memory module connected to the first central processing unit by a second channel, and a third memory module connected to the first central processing unit by a third channel may be provided. Each of the first memory module, the second memory module, and the third memory module may be configured to write the same data in a data area thereof and a mirroring data area thereof in response to an address in a mirroring mode.

公开(公告)号：US20210104292A1

公开(公告)日：2021-04-08

申请号：US16867631

申请日：2020-05-06

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Byoungsul KIM ,  Hokyong LEE ,  Hwajin JUNG ,  Yongjoo CHOI

IPC: G11C29/44 ,  G11C29/34 ,  G11C29/14 ,  G11C7/10

Abstract: A method for testing a memory chip including: performing an electrical die sorting (EDS) test on the memory chip; performing a package test when the EDS test is passed; performing a module test when the package test is passed; performing a mounting test when the module test is passed; and setting the memory chip to a mirroring mode through a fusing operation when the EDS test, tire package test, tire module test or the mounting test is failed.