公开(公告)号：US20230100119A1

公开(公告)日：2023-03-30

申请号：US17948858

申请日：2022-09-20

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Joonmin PARK ,  Byoungsul KIM ,  Hyunsoo SHIM

IPC: G06F3/06

Abstract: An operating method of a storage device including a non-volatile memory is provided. The operating method includes: receiving a first source voltage through a first voltage signal pin; based on the first source voltage different from a target voltage of the storage device, controlling the first source voltage to the target voltage; receiving a command, which indicates an information request associated with an operation voltage of the storage device, from a host; transmitting a response, which corresponds to the information request, to the host by using the storage device; receiving a second source voltage which has a voltage level different from the first source voltage, through the first voltage signal pin; and providing the second source voltage to the non-volatile memory.

公开(公告)号：US20220328122A1

公开(公告)日：2022-10-13

申请号：US17851255

申请日：2022-06-28

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Byoungsul KIM ,  Hokyong Lee ,  Hwajin Jung ,  Yongjoo Choi

IPC: G11C29/44 ,  G11C29/34 ,  G11C29/14 ,  G11C7/10

Abstract: A method for testing a memory chip including: performing an electrical die sorting (EDS) test on the memory chip; performing a package test when the EDS test is passed; performing a module test when the package test is passed; performing a mounting test when the module test is passed; and setting the memory chip to a mirroring mode through a fusing operation when the EDS test, the package test, the module test or the mounting test is failed.

公开(公告)号：US20230009061A1

公开(公告)日：2023-01-12

申请号：US17851794

申请日：2022-06-28

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hyunsoo SHIM ,  Byoungsul KIM ,  Joonmin PARK ,  Sungtack HONG

IPC: G06F3/06 ,  G11C11/4096 ,  G11C11/406

Abstract: Disclosed is a user system which includes a first device and a second device, which share a shared voltage, and a power management integrated circuit (PMIC) generating the shared voltage. An operation method of the user system includes performing a first operation of the first device, determining whether a second operation of the second device is to be performed while the first device performs the first operation, based on an operation profile, and when it is determined that the second operation of the second device is to be performed while the first device performs the first operation, changing a power mode of the PMIC from a first power mode to a second power mode, before the second device performs the second operation. The PMIC generates the shared voltage based on the first power mode or the second power mode.

公开(公告)号：US20210104291A1

公开(公告)日：2021-04-08

申请号：US16855373

申请日：2020-04-22

Applicant: Samsung Electronics Co., Ltd.

Inventor： Byoungsul KIM ,  Hokyong LEE ,  Dongjun KIM ,  Byungmin CHOI ,  Kideok HAN

IPC: G11C29/42 ,  G11C29/44 ,  G11C29/00 ,  G11C29/14 ,  G11C11/4091 ,  G11C11/4094 ,  G11C11/408

Abstract: A memory system including a first central processing unit, a first memory module connected to the first central processing unit by a first channel, a second memory module connected to the first central processing unit by a second channel, and a third memory module connected to the first central processing unit by a third channel may be provided. Each of the first memory module, the second memory module, and the third memory module may be configured to write the same data in a data area thereof and a mirroring data area thereof in response to an address in a mirroring mode.

公开(公告)号：US20210104292A1

公开(公告)日：2021-04-08

申请号：US16867631

申请日：2020-05-06

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Byoungsul KIM ,  Hokyong LEE ,  Hwajin JUNG ,  Yongjoo CHOI

IPC: G11C29/44 ,  G11C29/34 ,  G11C29/14 ,  G11C7/10

Abstract: A method for testing a memory chip including: performing an electrical die sorting (EDS) test on the memory chip; performing a package test when the EDS test is passed; performing a module test when the package test is passed; performing a mounting test when the module test is passed; and setting the memory chip to a mirroring mode through a fusing operation when the EDS test, tire package test, tire module test or the mounting test is failed.