公开(公告)号：US20240079355A1

公开(公告)日：2024-03-07

申请号：US18499527

申请日：2023-11-01

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jin-su LEE ,  Hong Sik CHAE ,  Youn Soo KIM ,  Tae Kyun KIM ,  Youn Joung CHO

IPC: H01L23/64 ,  H10B12/00

CPC classification number: H01L23/642 ,  H10B12/30

Abstract: Provided a semiconductor device comprises, a plurality of semiconductor patterns spaced in a first direction; a plurality of mold insulating layers between the plurality of semiconductor patterns, a plurality of silicide patterns contacting the plurality of semiconductor patterns; and a plurality of first metal conductive films between the plurality of mold insulating layers and connected to each of the silicide patterns, wherein each of the silicide patterns includes a first sidewall that faces the semiconductor pattern, and a second sidewall which faces the first metal conductive film, the first sidewall of the silicide pattern and the second sidewall of the silicide pattern extends in the first direction, and the first sidewall of the silicide pattern and the second sidewall of the silicide pattern are curved surfaces.

公开(公告)号：US20220093532A1

公开(公告)日：2022-03-24

申请号：US17470370

申请日：2021-09-09

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jin-su LEE ,  Hong Sik CHAE ,  Youn Soo KIM ,  Tae Kyun KIM ,  Youn Joung CHO

IPC: H01L23/64 ,  H01L27/108

Abstract: Provided a semiconductor device comprises, a plurality of semiconductor patterns spaced in a first direction; a plurality of mold insulating layers between the plurality of semiconductor patterns, a plurality of silicide patterns contacting the plurality of semiconductor patterns; and a plurality of first metal conductive films between the plurality of mold insulating layers and connected to each of the silicide patterns, wherein each of the silicide patterns includes a first sidewall that faces the semiconductor pattern, and a second sidewall which faces the first metal conductive film, the first sidewall of the silicide pattern and the second sidewall of the silicide pattern extends in the first direction, and the first sidewall of the silicide pattern and the second sidewall of the silicide pattern are curved surfaces.

公开(公告)号：US20240014252A1

公开(公告)日：2024-01-11

申请号：US18119896

申请日：2023-03-10

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hong Sik CHAE ,  Tae Kyun KIM ,  Ji Hoon AN ,  Hyun-Suk LEE ,  Gi Hee CHO ,  Jae Hyoung CHOI

IPC: H01L21/02

CPC classification number: H01L28/75 ,  H01L28/90 ,  H01L28/86

Abstract: A semiconductor device includes a substrate, first and second supporter patterns spaced vertically from the substrate, the second supporter pattern being spaced vertically from the first supporter pattern, a lower electrode hole extending vertically on the substrate, a lower electrode inside the lower electrode hole, contacting a sidewall of the first and second supporter patterns, the lower electrode including a first layer along a portion of a sidewall and bottom surface of the lower electrode hole, a second layer between the first layers, and a third layer on an upper surface of the first and second layers, the first and second layers including a material different from the second layer, and a sidewall of at least a portion of the third layer being concave toward the third layer, overlapping the second layer in the vertical direction, and being spaced apart from the second layer in the vertical direction.