公开(公告)号：US12131774B2

公开(公告)日：2024-10-29

申请号：US17968082

申请日：2022-10-18

申请人： SK hynix Inc.

发明人： Seung-Hwan Kim ,  Su-Ock Chung ,  Seon-Yong Cha

IPC分类号： G11C11/4097 ,  G11C7/18 ,  G11C11/401 ,  H10B12/00

CPC分类号： G11C11/4097 ,  G11C7/18 ,  G11C11/401 ,  H10B12/30

摘要： A memory device includes: a substrate; a bit line which is vertically oriented from the substrate; a plate line which is vertically oriented from the substrate; and a memory cell provided with a transistor and a capacitor that are positioned in a lateral arrangement between the bit line and the plate line, wherein the transistor includes: an active layer which is laterally oriented to be parallel to the substrate between the bit line and the capacitor; and a line-shaped lower word line and a line-shaped upper word line vertically stacked with the active layer therebetween and oriented to intersect with the active layer.

公开(公告)号：US12125873B2

公开(公告)日：2024-10-22

申请号：US17657641

申请日：2022-04-01

申请人： HeFeChip Corporation Limited

发明人： Liang Li ,  Chunhui Low ,  Huang Liu

IPC分类号： H01L21/84 ,  H01L21/8238 ,  H01L27/12 ,  H01L49/02 ,  H10B12/00

CPC分类号： H01L28/90 ,  H01L21/823821 ,  H01L21/845 ,  H01L27/1203 ,  H10B12/056 ,  H10B12/30 ,  H10B12/36 ,  H10B12/37

摘要： A method to form a fin structure on deep trenches (DTs) for a semiconductor device includes the following steps: A buried oxide layer (BOX) having the DTs, and silicon polies in the DTs is provided. A fin on the BOX and the silicon polies having poly fences is provided. A first mask is disposed on the fin. A liner is disposed on the BOX and the first mask, wherein the liner has a first part above the fin, a second part at lateral sides of the fin and a third part on the DTs and the BOX. A second mask is disposed on the first and the second parts of the liner. The second mask and the third parts of the liner are removed to reveal the first and the second parts of the liner. The poly fences are removed and spacers at the lateral sides are formed.

公开(公告)号：US20240347580A1

公开(公告)日：2024-10-17

申请号：US18135327

申请日：2023-04-17

申请人： NANYA TECHNOLOGY CORPORATION

发明人： PIN-JHU LI ,  SHIH-FAN KUAN

IPC分类号： H01L21/02 ,  H01L23/522

CPC分类号： H01L28/55 ,  H01L23/5223 ,  H01L28/60 ,  H10B12/03 ,  H10B12/30

摘要： A capacitor structure and a method of manufacturing a capacitor structure are provided. The capacitor structure includes a conductive via, an intermediate dielectric layer and a top electrode. The conductive via includes a neck portion located near a middle portion thereof. The intermediate dielectric layer is disposed on the conductive via. The top electrode is disposed on the intermediate dielectric layer.

公开(公告)号：US12120865B2

公开(公告)日：2024-10-15

申请号：US17132981

申请日：2020-12-23

申请人： Intel Corporation

发明人： Cheng-Ying Huang ,  Ashish Agrawal ,  Gilbert Dewey ,  Abhishek A. Sharma ,  Wilfred Gomes ,  Jack Kavalieros

IPC分类号： H10B12/00 ,  H01L21/683 ,  H01L29/06 ,  H01L29/423 ,  H01L29/66 ,  H01L29/786 ,  H10B53/30

CPC分类号： H10B12/30 ,  H01L21/6835 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/66742 ,  H01L29/78618 ,  H01L29/78696 ,  H10B12/03 ,  H10B12/05 ,  H10B53/30 ,  H01L2221/68363

摘要： Monolithic two-dimensional (2D) arrays of double-sided DRAM cells including a frontside bit cell over a backside bit cell. Each double-sided cell includes a stacked transistor structure having at least a first transistor over a second transistor. Each double-sided cell further includes a first capacitor on a frontside of the stacked transistor structure and electrically coupled to a source/drain of the first transistor. Each double-sided cell further includes a second capacitor on a backside of the stacked transistor structure and electrically coupled to a source/drain of the second transistor. Frontside cell addressing interconnects are electrically coupled to other terminals of at least the first transistor while one or more backside addressing interconnects are electrically coupled to at least one terminal of the second transistor or second capacitor.

公开(公告)号：US12114485B2

公开(公告)日：2024-10-08

申请号：US17669573

申请日：2022-02-11

申请人： CHANGXIN MEMORY TECHNOLOGIES, INC.

发明人： Qinghua Han

IPC分类号： H10B12/00 ,  H01L29/10 ,  H01L29/423 ,  H01L29/786

CPC分类号： H10B12/482 ,  H01L29/1041 ,  H01L29/42392 ,  H01L29/78696 ,  H10B12/30 ,  H10B12/488

摘要： Provided are a semiconductor structure and a method for manufacturing the same. The semiconductor structure includes: a base; a bit line; and a semiconductor channel including a first doped region, a channel region, and a second doped region that are sequentially arranged, where the first doped region contacts the bit line, and the first doped region, the channel region, and the second doped region are doped with first-type doped ions. The channel region is further doped with second-type doped ions, enabling a concentration of majority carriers in the channel region to be less than a concentration of majority carriers in the first doped region and a concentration of majority carriers in the second doped region. The first-type doped ions are one of N-type ions or P-type ions, and the second-type doped ions are the other of N-type ions or P-type ions.

公开(公告)号：US12114479B2

公开(公告)日：2024-10-08

申请号：US17368329

申请日：2021-07-06

申请人： Intel Corporation

发明人： Wilfred Gomes ,  Mauro J. Kobrinsky ,  Abhishek A. Sharma ,  Rajesh Kumar ,  Kinyip Phoa ,  Elliot Tan ,  Tahir Ghani ,  Swaminathan Sivakumar

IPC分类号： H10B12/00 ,  G11C5/06 ,  H01L23/522 ,  H01L23/528 ,  H01L27/06 ,  H01L29/786

CPC分类号： H10B12/31 ,  G11C5/063 ,  H01L23/5226 ,  H01L23/5283 ,  H01L27/0688 ,  H01L29/78696 ,  H10B12/30

摘要： A three-dimensional memory array may include a first memory array and a second memory array, stacked above the first. Some memory cells of the first array may be coupled to a first layer selector transistor, while some memory cells of the second array may be coupled to a second layer selector transistor. The first and second layer selector transistor may be coupled to one another and to a peripheral circuit that controls operation of the first and/or second memory arrays. A different layer selector transistor may be used for each row of memory cells of a given memory array and/or for each column of memory cells of a given memory array. Such designs may allow increasing density of memory cells in a memory array having a given footprint area, or, conversely, reducing the footprint area of the memory array with a given memory cell density.

公开(公告)号：US12108594B2

公开(公告)日：2024-10-01

申请号：US17370503

申请日：2021-07-08

申请人： CHANGXIN MEMORY TECHNOLOGIES, INC.

发明人： Jingwen Lu ,  Bingyu Zhu ,  Shijie Bai

IPC分类号： H10B12/00 ,  G11C5/06

CPC分类号： H10B12/485 ,  G11C5/063 ,  H10B12/03 ,  H10B12/30 ,  H10B12/482 ,  H10B12/50

摘要： A semiconductor manufacturing method includes: providing a semiconductor substrate, in which the semiconductor substrate includes an array region and a peripheral circuit region, in the array region, multiple capacitor contact holes are on the semiconductor substrate, and a first conductive layer is deposited on a bottom of each of the capacitor contact hole, and in the peripheral circuit region, a device layer is on the semiconductor substrate; treating the first conductive layer to increase its roughness; forming wire contact holes exposing the semiconductor substrate in the peripheral circuit region; forming a transition layer that at least covers a surface of the first conductive layer and a surface of the semiconductor substrate exposed by the wire contact holes; and forming a second conductive layer that covers the transition layer, and fills the capacitor contact holes and the wire contact holes.

公开(公告)号：US20240315000A1

公开(公告)日：2024-09-19

申请号：US18301270

申请日：2023-04-17

申请人： Winbond Electronics Corp.

发明人： Yi-Hsun Chung ,  Kai Jen

IPC分类号： H10B12/00

CPC分类号： H10B12/30 ,  H10B12/03 ,  H10B12/05

摘要： A memory structure includes a substrate structure and a memory cell disposed on the substrate structure. The memory cell includes device layers stacked on the substrate structure, a word line, a first contact, and a second contact. The device layer includes a semiconductor layer, a first doped region, a second doped region, a channel region located between the first doped region and the second doped region, and a capacitor. The first and second doped regions and the channel region are disposed in the semiconductor layer. The capacitor includes a first electrode layer, a second electrode layer, and a dielectric layer located between the first and second electrode layers. The word line is disposed on a sidewall of the channel layer. The first contact is electrically connected to the first doped regions. The second contact is electrically connected to the second electrode layers. A manufacturing method thereof is provided.

公开(公告)号：US12096617B2

公开(公告)日：2024-09-17

申请号：US17650130

申请日：2022-02-07

申请人： CHANGXIN MEMORY TECHNOLOGIES, INC.

发明人： Er-Xuan Ping ,  Jie Bai ,  Juanjuan Huang

IPC分类号： H01L27/108 ,  H10B12/00

CPC分类号： H10B12/482 ,  H10B12/30

摘要： A method of manufacturing a semiconductor structure and a semiconductor structure are disclosed in embodiments of the present disclosure. The method of manufacturing a semiconductor includes: providing a base; and forming an electrical contact layer, a bottom barrier layer, and a conductive layer that are sequentially stacked on the base, where a material of the conductive layer includes molybdenum.

公开(公告)号：US12089401B2

公开(公告)日：2024-09-10

申请号：US17575876

申请日：2022-01-14

申请人： CHANGXIN MEMORY TECHNOLOGIES, INC.

发明人： Jingwen Lu

IPC分类号： H10B12/00 ,  H01L21/768

CPC分类号： H10B12/482 ,  H01L21/76811 ,  H10B12/03 ,  H10B12/30

摘要： A preparation method of a semiconductor structure includes: providing a base; forming several bit lines arranged in parallel and at intervals on the base, which extend in a first direction; forming capacitor contact material layers between adjacent bit lines, upper surfaces of which are lower than upper surfaces of the bit lines; forming filling medium layers on the capacitor contact material layers; forming several first mask patterns arranged in parallel and at intervals on the filling medium layers and the bit lines, which extend in a second direction that intersects with the first direction; patterning the filling medium layers based on the first mask patterns to form several grooves in the filling medium layers; forming second mask patterns in the grooves; and patterning the capacitor contact material layers based on the second mask patterns to form several cylindrical capacitor contact structures arranged in parallel and at intervals.