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公开(公告)号:US20220336578A1
公开(公告)日:2022-10-20
申请号:US17857383
申请日:2022-07-05
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor: Gihee CHO , Sangyeol KANG , Jungoo KANG , Taekyun KIM , Jiwoon PARK , Sanghyuck AHN , Jin-Su LEE , Hyun-Suk LEE , Hongsik CHAE
IPC: H01L49/02 , H01L27/108
Abstract: A semiconductor device and a method of manufacturing the same, the device including a plurality of lower electrodes on a semiconductor substrate; a support pattern connecting the lower electrodes at sides of the lower electrodes; and a dielectric layer covering the lower electrodes and the support pattern, wherein each of the plurality of lower electrodes includes a pillar portion extending in a vertical direction perpendicular to a top surface of the semiconductor substrate; and a protrusion protruding from a sidewall of the pillar portion so as to be in contact with the support pattern, the pillar portion includes a conductive material, the protrusion includes a same conductive material as the pillar portion and is further doped with impurities.
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公开(公告)号:US20210134803A1
公开(公告)日:2021-05-06
申请号:US16903586
申请日:2020-06-17
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor: Gihee CHO , Jungoo KANG , Hyun-Suk LEE , Sanghyuck AHN
IPC: H01L27/108 , H01L21/02 , H01L49/02
Abstract: A semiconductor memory device includes a capacitor having a bottom electrode and a top electrode, a dielectric layer between the bottom and top electrodes, and an interface layer between the top electrode and the dielectric layer, the interface layer including a metal oxide and an additional constituent at a grain boundary of the interface layer.
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公开(公告)号:US20170069711A1
公开(公告)日:2017-03-09
申请号:US15212299
申请日:2016-07-18
Applicant: Samsung Electronics Co., Ltd.
Inventor: Jin-su LEE , Gihee CHO , DONGKYUN PARK , Hyun-Suk LEE , HEESOOK PARK , JONGMYEONG LEE
IPC: H01L49/02
CPC classification number: H01L28/75
Abstract: A semiconductor device is disclosed. The semiconductor device includes a substrate and capacitor electrically connected to the substrate. The capacitor includes a lower electrode, a dielectric layer disposed on the lower electrode, and an upper electrode disposed on the dielectric layer. The upper electrode includes a first electrode on the dielectric layer and a second electrode on the first electrode, such that the first electrode is disposed between the dielectric layer and the second electrode. The first electrode contains metal oxynitride having a formula of MxOyNz, in which an atomic ratio (y/x) of oxygen (O) to metallic element (M) is a value in the range from 0.5 to 2.
Abstract translation: 公开了一种半导体器件。 半导体器件包括电连接到衬底的衬底和电容器。 电容器包括下电极,设置在下电极上的电介质层和设置在电介质层上的上电极。 上电极包括介电层上的第一电极和第一电极上的第二电极,使得第一电极设置在电介质层和第二电极之间。 第一电极含有具有式MxOyNz的金属氧氮化物,其中氧(O)与金属元素(M)的原子比(y / x)为0.5至2的值。
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公开(公告)号:US20240014252A1
公开(公告)日:2024-01-11
申请号:US18119896
申请日:2023-03-10
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor: Hong Sik CHAE , Tae Kyun KIM , Ji Hoon AN , Hyun-Suk LEE , Gi Hee CHO , Jae Hyoung CHOI
IPC: H01L21/02
Abstract: A semiconductor device includes a substrate, first and second supporter patterns spaced vertically from the substrate, the second supporter pattern being spaced vertically from the first supporter pattern, a lower electrode hole extending vertically on the substrate, a lower electrode inside the lower electrode hole, contacting a sidewall of the first and second supporter patterns, the lower electrode including a first layer along a portion of a sidewall and bottom surface of the lower electrode hole, a second layer between the first layers, and a third layer on an upper surface of the first and second layers, the first and second layers including a material different from the second layer, and a sidewall of at least a portion of the third layer being concave toward the third layer, overlapping the second layer in the vertical direction, and being spaced apart from the second layer in the vertical direction.
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公开(公告)号:US20160380044A1
公开(公告)日:2016-12-29
申请号:US15064253
申请日:2016-03-08
Applicant: Samsung Electronics Co., Ltd.
Inventor: Hyun-Suk LEE , Jun-Goo KANG
CPC classification number: H01L28/75 , H01L27/0629 , H01L27/10852 , H01L28/90
Abstract: A capacitor may include a lower electrode structure, a dielectric layer on the lower electrode structure, and an upper electrode on the dielectric layer. The lower electrode structure may include first to third lower electrodes sequentially stacked, a first oxidation barrier pattern structure between the first lower electrode and the second lower electrode, and a second oxidation barrier pattern structure between the second lower electrode and the third lower electrode. The first oxidation barrier pattern structure may include first and second oxidation barrier patterns sequentially stacked on the first lower electrode, and the second oxidation barrier pattern structure may include third and fourth oxidation barrier patterns sequentially stacked on the second lower electrode.
Abstract translation: 电容器可以包括下电极结构,下电极结构上的电介质层和电介质层上的上电极。 下电极结构可以包括顺序层叠的第一至第三下电极,第一下电极和第二下电极之间的第一氧化阻挡图案结构,以及在第二下电极和第三下电极之间的第二氧化阻挡图案结构。 第一氧化屏障图案结构可以包括顺序层叠在第一下电极上的第一氧化阻挡图案和第二氧化屏障图案,第二氧化屏障图案结构可以包括顺序堆叠在第二下电极上的第三氧化阻挡图案和第四氧化阻挡图案。
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公开(公告)号:US20220216209A1
公开(公告)日:2022-07-07
申请号:US17701866
申请日:2022-03-23
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor: Gihee CHO , Jungoo KANG , Hyun-Suk LEE , Sanghyuck AHN
IPC: H01L27/108 , H01L49/02 , H01L21/02
Abstract: A semiconductor memory device includes a capacitor having a bottom electrode and a top electrode, a dielectric layer between the bottom and top electrodes, and an interface layer between the top electrode and the dielectric layer, the interface layer including a metal oxide and an additional constituent at a grain boundary of the interface layer.
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公开(公告)号:US20220037461A1
公开(公告)日:2022-02-03
申请号:US17189700
申请日:2021-03-02
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor: Gihee CHO , Sangyeol KANG , Jungoo KANG , Taekyun KIM , Jiwoon PARK , Sanghyuck AHN , Jin-Su LEE , Hyun-Suk LEE , Hongsik CHAE
IPC: H01L49/02 , H01L27/108
Abstract: A semiconductor device and a method of manufacturing the same, the device including a plurality of lower electrodes on a semiconductor substrate; a support pattern connecting the lower electrodes at sides of the lower electrodes; and a dielectric layer covering the lower electrodes and the support pattern, wherein each of the plurality of lower electrodes includes a pillar portion extending in a vertical direction perpendicular to a top surface of the semiconductor substrate; and a protrusion protruding from a sidewall of the pillar portion so as to be in contact with the support pattern, the pillar portion includes a conductive material, the protrusion includes a same conductive material as the pillar portion and is further doped with impurities.
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