SEMICONDUCTOR DEVICE AND MEMORY SYSTEM

    公开(公告)号:US20220059155A1

    公开(公告)日:2022-02-24

    申请号:US17230519

    申请日:2021-04-14

    Abstract: A semiconductor device includes: a multi-level receiver including N sense amplifiers and a decoder decoding an output of the N sense amplifiers, each of the N sense amplifiers receiving a multi-level signal having M levels and a reference signal (where M is a natural number, higher than 2, and where N is a natural number, lower than M); a clock buffer receiving a reference clock signal; and a clock controller generating N clock signals using the reference clock signal, inputting the N clock signals to the N sense amplifiers, respectively, and individually determining a phase of each of the N clock signals using the output of the N sense amplifiers.

Patent Agency Ranking