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公开(公告)号:US20210242870A1
公开(公告)日:2021-08-05
申请号:US17021728
申请日:2020-09-15
Applicant: Samsung Electronics Co., Ltd.
Inventor: Tongsung KIM , Youngmin JO , Jungjune PARK , Jindo BYUN , Dongho SHIN , Jeongdon IHM
IPC: H03K19/00 , H03K19/0185 , H03K19/08 , G11C7/10 , G11C8/10
Abstract: An impedance calibration circuit includes a first code generation circuit connected to a first reference resistor, and configured to generate a first code for forming a resistance based on the first reference resistor, by using the first reference resistor; a second code generation circuit configured to form a resistance of a second reference resistor less than the resistance of the first reference resistor, based on the first code, and generate a second code by using the second reference resistor; and a target impedance code generation circuit configured to generate a target impedance code based on the first code, the second code, and a target impedance value, and form an impedance having the target impedance value in a termination driver connected to the impedance calibration circuit, based on the target impedance code.
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公开(公告)号:US20240203466A1
公开(公告)日:2024-06-20
申请号:US18230776
申请日:2023-08-07
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor: Junyoung PARK , Garam KIM , Joohwan KIM , Jindo BYUN , Eunseok SHIN , Hyunyoon CHO , Junghwan CHOI
IPC: G11C7/10 , H03K19/017
CPC classification number: G11C7/1066 , G11C7/1063 , H03K19/01742
Abstract: A transmitter configured to receive first to N-th data in parallel and sequentially output the first to N-th data in response to first to N-th clock signals having different phases from each other, where N is an integer of at least 2, the transmitter including first to N-th data selectors including a first data selector and a second data selector in correspondence to the first to N-th data, each of the first to N-th data selectors being configured to perform a logical operation on one of the first to N-th data and the first to N-th clock signals and output a plurality of data selection signals, a first pre-driver in correspondence to at least two data selectors among the first to N-th data selectors, the first pre-driver being configured to receive the plurality of data selection signals from the at least two data selectors.
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公开(公告)号:US20220157353A1
公开(公告)日:2022-05-19
申请号:US17361780
申请日:2021-06-29
Applicant: Samsung Electronics Co., Ltd.
Inventor: Joohwan KIM , Jindo BYUN , Younghoon SON , Youngdon CHOI , Junghwan CHOI
Abstract: A memory package includes a package substrate including a redistribution layer and bonding pads connected to the redistribution layer, the redistribution layer including a plurality of signal paths; a buffer chip mounted on the package substrate and including a plurality of chip pads corresponding to a plurality of memory channels; and a plurality of memory chips stacked on the package substrate and divided into a plurality of groups corresponding to the plurality of memory channels, wherein memory chips of a first group, among the plurality of memory chips, are connected to first chip pads of the plurality of chip pads through first wires, and wherein memory chips of a second group, among the plurality of memory chips, are connected to second chip pads of the plurality of chip pads through second wires and at least a portion of the plurality of signal paths.
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公开(公告)号:US20220414032A1
公开(公告)日:2022-12-29
申请号:US17903240
申请日:2022-09-06
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor: Hyungmin JIN , Jindo BYUN , Younghoon SON , Youngdon CHOI , Junghwan CHOI
Abstract: A memory system including: a memory controller to transmit a command, an address, or data to a first channel based on a data input/output signal having one of N (N is a natural number of three or more) different voltage levels during a first time interval, the memory controller transmitting the command, the address, or the data not transmitted during the first time interval to the first channel based on the data input/output signal having one of two different voltage levels during a second time interval; and a memory device to sample the data input/output signal received via the first channel during the first time interval in a pulse amplitude modulation (PAM)-N mode, the memory device sampling the data input/output signal received via the first channel during the second time interval in a non return to zero (NRZ) mode.
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公开(公告)号:US20220059155A1
公开(公告)日:2022-02-24
申请号:US17230519
申请日:2021-04-14
Applicant: Samsung Electronics Co., Ltd.
Inventor: Hyeokjun CHOI , Jindo BYUN , Yonghoon SON , Youngdon CHOI , Junghwan CHOI
IPC: G11C11/4091 , G11C11/4076 , G11C11/408 , G11C11/4096 , G11C11/406
Abstract: A semiconductor device includes: a multi-level receiver including N sense amplifiers and a decoder decoding an output of the N sense amplifiers, each of the N sense amplifiers receiving a multi-level signal having M levels and a reference signal (where M is a natural number, higher than 2, and where N is a natural number, lower than M); a clock buffer receiving a reference clock signal; and a clock controller generating N clock signals using the reference clock signal, inputting the N clock signals to the N sense amplifiers, respectively, and individually determining a phase of each of the N clock signals using the output of the N sense amplifiers.
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公开(公告)号:US20240212746A1
公开(公告)日:2024-06-27
申请号:US18541218
申请日:2023-12-15
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor: Minsu JUNG , Jindo BYUN , Joohwan KIM , Eun Seok SHIN , Hyun-Yoon CHO , Junghwan CHOI
IPC: G11C11/4096 , G11C11/4093 , H03K19/017
CPC classification number: G11C11/4096 , G11C11/4093 , H03K19/01742 , G11C2207/2254
Abstract: Disclosed is a memory device which includes a pull-up driver that is connected between a power supply voltage and a first node, a T-coil circuit that is connected between the first node and a second node, an external resistor, and a ZQ controller that performs a ZQ calibration operation on the pull-up driver. The ZQ controller includes a path selecting circuit that selects one node among the first node and the second node, a comparing circuit that compares a voltage of the one node selected by the path selecting circuit with a pull-up reference voltage and outputs a comparison result, and a code generating circuit that generates a pull-up code for driving the pull-up driver, based on the comparison result. While the pull-up code is generated, the external resistor is connected between the second node and a ground voltage.
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公开(公告)号:US20220121582A1
公开(公告)日:2022-04-21
申请号:US17326513
申请日:2021-05-21
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor: Hyungmin JIN , Jindo BYUN , Younghoon SON , Youngdon CHOI , Junghwan CHOI
Abstract: A memory system including: a memory controller to transmit a command, an address, or data to a first channel based on a data input/output signal having one of N (N is a natural number of three or more) different voltage levels during a first time interval, the memory controller transmitting the command, the address, or the data not transmitted during the first time interval to the first channel based on the data input/output signal having one of two different voltage levels during a second time interval; and a memory device to sample the data input/output signal received via the first channel during the first time interval in a pulse amplitude modulation (PAM)-N mode, the memory device sampling the data input/output signal received via the first channel during the second time interval in a non return to zero (NRZ) mode.
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公开(公告)号:US20210359684A1
公开(公告)日:2021-11-18
申请号:US17389148
申请日:2021-07-29
Applicant: Samsung Electronics Co., Ltd.
Inventor: Tongsung KIM , Youngmin JO , Jungjune PARK , Jindo BYUN , Dongho SHIN , Jeongdon IHM
IPC: H03K19/00 , H03K19/0185 , G11C7/10 , G11C8/10 , H03K19/08
Abstract: An impedance calibration circuit includes a first code generation circuit connected to a first reference resistor, and configured to generate a first code for forming a resistance based on the first reference resistor, by using the first reference resistor; a second code generation circuit configured to form a resistance of a second reference resistor less than the resistance of the first reference resistor, based on the first code, and generate a second code by using the second reference resistor; and a target impedance code generation circuit configured to generate a target impedance code based on the first code, the second code, and a target impedance value, and form an impedance having the target impedance value in a termination driver connected to the impedance calibration circuit, based on the target impedance code.
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公开(公告)号:US20240370386A1
公开(公告)日:2024-11-07
申请号:US18772354
申请日:2024-07-15
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor: Hyungmin JIN , Jindo BYUN , Younghoon SON , Youngdon CHOI , Junghwan CHOI
Abstract: A memory system including: a memory controller to transmit a command, an address, or data to a first channel based on a data input/output signal having one of N (N is a natural number of three or more) different voltage levels during a first time interval, the memory controller transmitting the command, the address, or the data not transmitted during the first time interval to the first channel based on the data input/output signal having one of two different voltage levels during a second time interval; and a memory device to sample the data input/output signal received via the first channel during the first time interval in a pulse amplitude modulation (PAM)-N mode, the memory device sampling the data input/output signal received via the first channel during the second time interval in a non return to zero (NRZ) mode.
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公开(公告)号:US20240187002A1
公开(公告)日:2024-06-06
申请号:US18350606
申请日:2023-07-11
Applicant: Samsung Electronics Co., Ltd.
Inventor: Jinwook LEE , Joohwan KIM , Junyoung PARK , Jindo BYUN , Eunseok SHIN , Junghwan CHOI
CPC classification number: H03L7/0812 , G11C7/222 , H03K5/135
Abstract: A semiconductor device includes a phase splitter configured to output a plurality of clock signals having different phases by using a plurality of external clock signals having different phases, a plurality of code generators configured to receive a pair of selection clock signals determined from the plurality of clock signals and to output a phase code corresponding to a phase difference error between the pair of selection clock signals, and a delay circuit configured to at least partly simultaneously adjust at least two of a rising edge and a falling edge of each of the plurality of external clock signals with reference to the phase code during a lock time.
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