中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

7 records (took 0.017 seconds)

    SEMICONDUCTOR DEVICE INCLUDING DATA STORAGE PATTERN
    1.
    发明申请
    SEMICONDUCTOR DEVICE INCLUDING DATA STORAGE PATTERN 有权

    公开(公告)号：US20220344356A1

    公开(公告)日：2022-10-27

    申请号：US17858672

    申请日：2022-07-06

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Yonghoon SON

    IPC: H01L27/1157 ,  H01L27/11578 ,  H01L27/11565

    Abstract: A semiconductor device includes a vertical pattern in a first direction, interlayer insulating layers, spaced apart, a side surface of each of the interlayer insulating layers facing a side of the vertical pattern, a gate electrode between the interlayer insulating layers, a side of the gate electrode facing the side of the vertical pattern, a dielectric structure between the vertical pattern and the interlayer insulating layers with the gate electrode between the interlayer insulating layers, and data storage patterns between the gate electrode and the vertical pattern, the data storage patterns spaced apart. The dielectric structure includes a first and a second dielectric layers, the second dielectric layer between the first dielectric layer and the vertical pattern. The data storage patterns are between the first dielectric layer and the second dielectric layer. The first dielectric layer includes portions between the data storage patterns and the gate electrode.

    VERTICAL NON-VOLATILE MEMORY DEVICE
    2.
    发明申请
    VERTICAL NON-VOLATILE MEMORY DEVICE 有权

    公开(公告)号：US20230109996A1

    公开(公告)日：2023-04-13

    申请号：US17955696

    申请日：2022-09-29

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Yonghoon SON ,  Sukkang SUNG ,  Sangdon LEE ,  Euntaek JUNG

    IPC: H01L27/11582 ,  H01L23/535 ,  H01L27/11573

    Abstract: A vertical non-volatile memory device includes, a substrate, a contact gate stack structure including a plurality of gate lines stacked in a vertical direction on the substrate, the vertical direction being perpendicular to a surface of the substrate, a plurality of insulating layers between the gate lines, a plurality of separation insulating layers in contact with a protruding end of each of the plurality of gate lines, respectively, in a horizontal direction at both sides of a contact hole, wherein the contact hole extends in the vertical direction in the contact gate stack structure so that the protruding ends of the plurality of gate lines protrude from an inner wall of the contact hole, the horizontal direction being horizontal to the surface of the substrate, and a contact electrode at the contact hole and electrically connected to an uppermost gate line among the plurality of gate lines.

    SEMICONDUCTOR DEVICES AND DATA STORAGE SYSTEMS INCLUDING THE SAME
    4.
    发明申请
    SEMICONDUCTOR DEVICES AND DATA STORAGE SYSTEMS INCLUDING THE SAME 有权

    公开(公告)号：US20230046500A1

    公开(公告)日：2023-02-16

    申请号：US17717844

    申请日：2022-04-11

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Yonghoon SON

    IPC: H01L27/11582 ,  H01L27/11556 ,  H01L29/423

    Abstract: A semiconductor device includes a semiconductor structure that includes a substrate having a first region and a second region, gate electrodes stacked and spaced apart from each other in a first direction, extend at different lengths in a second direction on the second region, and include pad regions, interlayer insulating layers alternately stacked with the gate electrodes, channel structures penetrating the gate electrodes, extending in the first direction, and each including a channel layer, contact plugs penetrating the pad regions and extending in the first direction on the second region, and contact insulating layers between the gate electrodes and between ones of the contact plugs below the pad regions. The pad regions and the contact insulating layers protrude from the interlayer insulating layers toward the contact plugs in a horizontal direction.

    SEMICONDUCTOR DEVICE AND MEMORY SYSTEM
    6.
    发明申请
    SEMICONDUCTOR DEVICE AND MEMORY SYSTEM 有权

    公开(公告)号：US20220059155A1

    公开(公告)日：2022-02-24

    申请号：US17230519

    申请日：2021-04-14

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Hyeokjun CHOI ,  Jindo BYUN ,  Yonghoon SON ,  Youngdon CHOI ,  Junghwan CHOI

    IPC: G11C11/4091 ,  G11C11/4076 ,  G11C11/408 ,  G11C11/4096 ,  G11C11/406

    Abstract: A semiconductor device includes: a multi-level receiver including N sense amplifiers and a decoder decoding an output of the N sense amplifiers, each of the N sense amplifiers receiving a multi-level signal having M levels and a reference signal (where M is a natural number, higher than 2, and where N is a natural number, lower than M); a clock buffer receiving a reference clock signal; and a clock controller generating N clock signals using the reference clock signal, inputting the N clock signals to the N sense amplifiers, respectively, and individually determining a phase of each of the N clock signals using the output of the N sense amplifiers.

Patent Agency Ranking