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    CLOCK SIGNAL DELAY PATH UNIT AND SEMICONDUCTOR MEMORY DEVICE INCLUDING THE SAME
    3.
    发明申请
    CLOCK SIGNAL DELAY PATH UNIT AND SEMICONDUCTOR MEMORY DEVICE INCLUDING THE SAME 有权

    公开(公告)号：US20230072675A1

    公开(公告)日：2023-03-09

    申请号：US17695168

    申请日：2022-03-15

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Mingyu LEE ,  Youngchul CHO ,  Seungjin PARK ,  Youngdon CHOI ,  Junghwan CHOI

    IPC: H03K5/06 ,  H03K5/15 ,  H03K5/05

    Abstract: A clock signal delay path unit includes a first delay cell including a first root signal line for delaying and transmitting a clock signal, a first repeater to transmit the clock signal transmitted through the first root signal line without signal attenuation, and a second root signal line for delaying and transmitting the clock signal output from the first repeater, a second delay cell including a first inverting circuit configured to invert the clock signal provided from the first delay cell to generate an inverted clock signal, and a third delay cell including a first branch signal line for delaying and transmitting the inverted clock signal provided from the second delay cell, a second repeater to transmit the inverted clock signal transmitted through the first branch signal line, and a second branch signal line for delaying and transmitting the inverted clock signal output from the second repeater.

    TRANSMITTER, MEMORY DEVICE AND SEMICONDUCTOR DEVICE INCLUDING THE TRANSMITTER
    8.
    发明公开
    TRANSMITTER, MEMORY DEVICE AND SEMICONDUCTOR DEVICE INCLUDING THE TRANSMITTER 审中-公开

    公开(公告)号：US20240203466A1

    公开(公告)日：2024-06-20

    申请号：US18230776

    申请日：2023-08-07

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Junyoung PARK ,  Garam KIM ,  Joohwan KIM ,  Jindo BYUN ,  Eunseok SHIN ,  Hyunyoon CHO ,  Junghwan CHOI

    IPC: G11C7/10 ,  H03K19/017

    CPC classification number: G11C7/1066 ,  G11C7/1063 ,  H03K19/01742

    Abstract: A transmitter configured to receive first to N-th data in parallel and sequentially output the first to N-th data in response to first to N-th clock signals having different phases from each other, where N is an integer of at least 2, the transmitter including first to N-th data selectors including a first data selector and a second data selector in correspondence to the first to N-th data, each of the first to N-th data selectors being configured to perform a logical operation on one of the first to N-th data and the first to N-th clock signals and output a plurality of data selection signals, a first pre-driver in correspondence to at least two data selectors among the first to N-th data selectors, the first pre-driver being configured to receive the plurality of data selection signals from the at least two data selectors.

    LOW DROPOUT REGULATOR AND MEMORY DEVICE INCLUDING THE SAME
    10.
    发明申请
    LOW DROPOUT REGULATOR AND MEMORY DEVICE INCLUDING THE SAME 有权

    公开(公告)号：US20230045744A1

    公开(公告)日：2023-02-09

    申请号：US17709853

    申请日：2022-03-31

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Jinook JUNG ,  Jaewoo PARK ,  Junhan CHOI ,  Myoungbo KWAK ,  Junghwan CHOI

    IPC: G05F1/575 ,  G11C11/4074 ,  G11C11/4093 ,  G11C11/4076

    Abstract: Disclosed is a low dropout regulator which includes a first resistor, a first transistor including a gate terminal connected with a first end of the first resistor, a source terminal connected with a power supply voltage terminal, and a drain terminal connected with a first node, an operational amplifier including input terminals respectively connected with a reference voltage and the first node and an output terminal, a second transistor including a gate terminal connected with the output terminal of the operational amplifier, a source terminal connected with the first node, and a drain terminal connected with a second node, a third transistor including a gate terminal connected with a second end of the first resistor, a source terminal connected with the power supply voltage terminal, and a drain terminal connected with a third node, and a current source connected between the second node and a ground voltage terminal.

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