中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

10 records (took 0.014 seconds)

    Semiconductor devices
    2.
    发明授权
    Semiconductor devices 有权

    公开(公告)号：US11127730B2

    公开(公告)日：2021-09-21

    申请号：US16539474

    申请日：2019-08-13

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Inhak Lee ,  Sang-Yeop Baeck ,  JaeSeung Choi ,  Hyunsu Choi ,  SangShin Han

    IPC: H01L27/02 ,  H01L23/528 ,  H01L21/8238 ,  H01L23/522 ,  H01L27/11 ,  H01L27/092 ,  G06F30/398 ,  H01L29/78 ,  G06F30/392 ,  G06F30/394

    Abstract: A semiconductor device including memory cell transistors on a substrate is provided. The semiconductor device includes a first wiring layer on the memory cell transistors and including a bit line and a first conductive pattern, a second wiring layer on the first wiring layer and including a ground line, a first via interposed between and electrically connecting the bit line and a source/drain of a first memory cell transistor among the memory cell transistors, and a first extended via interposed between the ground line and a source/drain of a second memory cell transistor among the memory cell transistors. The ground line is electrically connected to the source/drain of the second memory cell transistor through the first extended via and the first conductive pattern. The first extended via has a width greater than that of the first via.

    MEMORY DEVICES COMPRISING A WRITE ASSIST CIRCUIT
    7.
    发明申请
    MEMORY DEVICES COMPRISING A WRITE ASSIST CIRCUIT 审中-公开

    公开(公告)号：US20180294018A1

    公开(公告)日：2018-10-11

    申请号：US15840601

    申请日：2017-12-13

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Sang-Yeop Baeck ,  Inhak Lee ,  SangShin Han ,  Tae-Hyung Kim ,  JaeSeung Choi ,  Sunghyun Park ,  Hyunsu Choi

    IPC: G11C7/10 ,  G11C11/419 ,  G11C11/4096 ,  G11C7/12 ,  G11C11/412 ,  G11C5/14 ,  G11C8/08 ,  G11C8/16

    Abstract: A memory device includes a first write assist circuit providing a cell voltage or a write assist voltage to a first memory cell connected with a first bit line pair, a first write driver that provides write data to the first memory cell through the first bit line pair, a second write assist circuit that provides the cell voltage or the write assist voltage to a second memory cell connected with a second bit line pair, and a second write driver that provides write data to the second memory cell through the second bit line pair. One of the first and second write assist circuits provides the write assist voltage in response to a column selection signal for selecting one write driver, which provides write data, from among the first, and second write drivers, and the other thereof provides the cell voltage in response to the column selection signal.

    Semiconductor devices
    9.
    发明授权
    Semiconductor devices 有权

    公开(公告)号：US10424577B2

    公开(公告)日：2019-09-24

    申请号：US15842995

    申请日：2017-12-15

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Inhak Lee ,  Sang-Yeop Baeck ,  JaeSeung Choi ,  Hyunsu Choi ,  SangShin Han

    IPC: H01L27/02 ,  H01L27/092 ,  H01L27/11 ,  H01L23/522 ,  H01L23/528 ,  H01L21/8238 ,  G06F17/50 ,  H01L29/78

    Abstract: A semiconductor device including memory cell transistors on a substrate is provided. The semiconductor device includes a first wiring layer on the memory cell transistors and including a bit line and a first conductive pattern, a second wiring layer on the first wiring layer and including a ground line, a first via interposed between and electrically connecting the bit line and a source/drain of a first memory cell transistor among the memory cell transistors, and a first extended via interposed between the ground line and a source/drain of a second memory cell transistor among the memory cell transistors. The ground line is electrically connected to the source/drain of the second memory cell transistor through the first extended via and the first conductive pattern. The first extended via has a width greater than that of the first via.

    System on chip including dual power rail and voltage supply method thereof
    10.
    发明授权
    System on chip including dual power rail and voltage supply method thereof 有权
    片上系统包括双电源轨及其电压供电方式

    公开(公告)号：US09001572B2

    公开(公告)日：2015-04-07

    申请号：US14255638

    申请日：2014-04-17

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Hyunsu Choi ,  Jaeseung Choi ,  Gyuhong Kim ,  Dong-Wook Seo

    IPC: G11C16/04 ,  G11C11/419 ,  G11C5/14

    CPC classification number: G11C11/419 ,  G11C5/14 ,  G11C5/147 ,  G11C11/417

    Abstract: A system on chip includes an SRAM. The SRAM includes at least one memory cell and a peripheral circuit accessing the at least memory cell. A first power circuit is configured to supply a first driving voltage to the at least one memory cell. A second power circuit is configured to supply a second driving voltage to the peripheral circuit. The SRAM further includes an auto power switch that selects the higher of the first driving voltage and the second driving voltage and supplies the selected voltage to the at least one memory cell.

    Abstract translation: 片上系统包括SRAM。 SRAM包括至少一个存储器单元和至少存储至少存储单元的外围电路。 第一电源电路被配置为向所述至少一个存储器单元提供第一驱动电压。 第二电源电路被配置为向外围电路提供第二驱动电压。 SRAM还包括自动电源开关，其选择较高的第一驱动电压和第二驱动电压，并将所选择的电压提供给至少一个存储单元。

Patent Agency Ranking