公开(公告)号：US09524772B2

公开(公告)日：2016-12-20

申请号：US14793053

申请日：2015-07-07

Applicant: Samsung Electronics Co., Ltd.

Inventor： Woojin Rim ,  Taejoong Song ,  Gyuhong Kim ,  Jongsun Park ,  Woong Choi

IPC: G11C5/06 ,  G11C7/06 ,  G11C5/14 ,  G11C7/02 ,  G11C8/00 ,  G11C11/419 ,  G11C11/412 ,  G11C7/12

CPC classification number: G11C11/419 ,  G11C7/12 ,  G11C11/412 ,  G11C2207/002

Abstract: A memory device includes a first memory cell array including memory cells of a single-ended bitline structure, a second memory cell array including memory cells of a single-ended bitline structure, a reference voltage generator configured to output a bitline voltage of a selected one of the first and second memory cell arrays as a sensing voltage according to an array select signal and output a bitline voltage of an unselected memory cell array as a reference voltage, and a differential sense amplifier configured to amplify and output a difference between the sensing voltage and the reference voltage. Logic states of the sensing voltage and the reference voltage are complementary to each other.

Abstract translation: 存储器件包括包括单端位线结构的存储器单元的第一存储单元阵列，包括单端位线结构的存储单元的第二存储单元阵列，配置为输出所选择的位线的位线电压的参考电压发生器 的第一和第二存储单元阵列作为根据阵列选择信号的感测电压，并输出未选择的存储单元阵列的位线电压作为参考电压;以及差分读出放大器，被配置为放大和输出感测电压 和参考电压。 感测电压和参考电压的逻辑状态彼此互补。

公开(公告)号：US09001572B2

公开(公告)日：2015-04-07

申请号：US14255638

申请日：2014-04-17

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hyunsu Choi ,  Jaeseung Choi ,  Gyuhong Kim ,  Dong-Wook Seo

IPC: G11C16/04 ,  G11C11/419 ,  G11C5/14

CPC classification number: G11C11/419 ,  G11C5/14 ,  G11C5/147 ,  G11C11/417

Abstract: A system on chip includes an SRAM. The SRAM includes at least one memory cell and a peripheral circuit accessing the at least memory cell. A first power circuit is configured to supply a first driving voltage to the at least one memory cell. A second power circuit is configured to supply a second driving voltage to the peripheral circuit. The SRAM further includes an auto power switch that selects the higher of the first driving voltage and the second driving voltage and supplies the selected voltage to the at least one memory cell.

Abstract translation: 片上系统包括SRAM。 SRAM包括至少一个存储器单元和至少存储至少存储单元的外围电路。 第一电源电路被配置为向所述至少一个存储器单元提供第一驱动电压。 第二电源电路被配置为向外围电路提供第二驱动电压。 SRAM还包括自动电源开关，其选择较高的第一驱动电压和第二驱动电压，并将所选择的电压提供给至少一个存储单元。

公开(公告)号：US20160042785A1

公开(公告)日：2016-02-11

申请号：US14793053

申请日：2015-07-07

Applicant: Samsung Electronics Co., Ltd.

Inventor： Woojin Rim ,  Taejoong Song ,  Gyuhong Kim ,  Jongsun Park ,  Woong Choi

IPC: G11C11/419 ,  G11C11/418

CPC classification number: G11C11/419 ,  G11C7/12 ,  G11C11/412 ,  G11C2207/002

Abstract: A memory device includes a first memory cell array including memory cells of a single-ended bitline structure, a second memory cell array including memory cells of a single-ended bitline structure, a reference voltage generator configured to output a bitline voltage of a selected one of the first and second memory cell arrays as a sensing voltage according to an array select signal and output a bitline voltage of an unselected memory cell array as a reference voltage, and a differential sense amplifier configured to amplify and output a difference between the sensing voltage and the reference voltage. Logic states of the sensing voltage and the reference voltage are complementary to each other.

Abstract translation: 存储器件包括包括单端位线结构的存储器单元的第一存储单元阵列，包括单端位线结构的存储单元的第二存储单元阵列，配置为输出所选择的位线的位线电压的参考电压发生器 的第一和第二存储单元阵列作为根据阵列选择信号的感测电压，并输出未选择的存储单元阵列的位线电压作为参考电压;以及差分读出放大器，被配置为放大和输出感测电压 和参考电压。 感测电压和参考电压的逻辑状态彼此互补。

公开(公告)号：US09496027B2

公开(公告)日：2016-11-15

申请号：US14793044

申请日：2015-07-07

Applicant: Samsung Electronics Co., Ltd.

Inventor： Woojin Rim ,  Taejoong Song ,  Gyuhong Kim ,  Seong Ook Jung ,  Hanwool Jeong

IPC: G11C11/412 ,  G11C11/419

CPC classification number: G11C11/419

Abstract: A static random access memory device may include a write driver configured to float one of a first bitline and a second bitline connected to a memory cell and apply a write voltage to the other bitline in response to a logic state of a data signal; a write failure detector configured to receive a voltage of the floated bitline and output a write failure signal; and an assist voltage generator configured to generate a write assist voltage in response to the write failure signal. The write driver may additionally provide the write assist voltage to a bitline to which the write voltage is applied.

Abstract translation: 静态随机存取存储器装置可以包括写入驱动器，其被配置为浮置连接到存储器单元的第一位线和第二位线之一，并响应于数据信号的逻辑状态向另一个位线施加写入电压; 写入故障检测器，被配置为接收浮动位线的电压并输出写入失败信号; 以及辅助电压发生器，被配置为响应于写入失败信号产生写入辅助电压。 写入驱动器可以另外向写入电压施加到的位线提供写入辅助电压。

公开(公告)号：US20160042784A1

公开(公告)日：2016-02-11

申请号：US14793044

申请日：2015-07-07

Applicant: Samsung Electronics Co., Ltd.

Inventor： Woojin Rim ,  Taejoong Song ,  Gyuhong Kim ,  Seong Ook Jung ,  Hanwool Jeong

IPC: G11C11/419 ,  G11C29/02

CPC classification number: G11C11/419

Abstract: A static random access memory device may include a write driver configured to float one of a first bitline and a second bitline connected to a memory cell and apply a write voltage to the other bitline in response to a logic state of a data signal; a write failure detector configured to receive a voltage of the floated bitline and output a write failure signal; and an assist voltage generator configured to generate a write assist voltage in response to the write failure signal. The write driver may additionally provide the write assist voltage to a bitline to which the write voltage is applied.

Abstract translation: 静态随机存取存储器装置可以包括写入驱动器，其被配置为浮置连接到存储器单元的第一位线和第二位线之一，并响应于数据信号的逻辑状态向另一个位线施加写入电压; 写入故障检测器，被配置为接收浮动位线的电压并输出写入失败信号; 以及辅助电压发生器，被配置为响应于写入失败信号产生写入辅助电压。 写入驱动器可以另外向写入电压施加到的位线提供写入辅助电压。