公开(公告)号：US20220320043A1

公开(公告)日：2022-10-06

申请号：US17529798

申请日：2021-11-18

Applicant: Samsung Electronics Co., Ltd.

Inventor： JAEKYUNG YOO ,  JONGHO LEE ,  YEONGKWON KO

IPC: H01L25/065 ,  H01L23/00 ,  H01L23/31 ,  H01L23/367 ,  H01L25/00 ,  H01L21/48 ,  H01L21/56 ,  H01L23/498 ,  H01L23/538

Abstract: A semiconductor package includes a lower substrate including a central region and an edge region, an upper substrate on the central region of the lower substrate, a first semiconductor chip on the upper substrate, a second semiconductor chip on the upper substrate and horizontally spaced apart from the first semiconductor chip, a reinforcing structure on the edge region of the lower substrate, and a molding layer that covers an inner sidewall of the reinforcing structure, a top surface of the lower substrate, a sidewall of the first semiconductor chip, a sidewall of the second semiconductor chip, and the upper substrate. The molding layer is interposed between the lower substrate and the upper substrate, between the upper substrate and the first semiconductor chip, and between the upper substrate and the second semiconductor chip. The first semiconductor chip is of a different type from the second semiconductor chip.

公开(公告)号：US20220293563A1

公开(公告)日：2022-09-15

申请号：US17405130

申请日：2021-08-18

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： YEONGKWON KO ,  JINWOO PARK ,  JAEKYUNG YOO ,  TEAKHOON LEE

IPC: H01L25/065 ,  H01L21/56 ,  H01L25/00 ,  H01L23/00

Abstract: A semiconductor package includes a package substrate on which a base chip is disposed. A first semiconductor chip is disposed on the base chip. A second semiconductor chip is disposed on the first semiconductor chip. An inner mold layer surrounds an upper surface of the base chip and respective side surfaces of the first semiconductor chip and the second semiconductor chip. A first outer mold layer is interposed between the package substrate and the base chip while covering at least a portion of a side surface of the base chip. A second outer mold layer is disposed on the first outer mold layer while covering at least a portion of a side surface of the inner mold layer. The second outer mold layer is spaced apart from the package substrate. The first outer mold layer and the second outer mold layer have different viscosities.

公开(公告)号：US20210028098A1

公开(公告)日：2021-01-28

申请号：US16787107

申请日：2020-02-11

Applicant: Samsung Electronics Co., Ltd.

Inventor： JAEKYUNG YOO ,  JAEEUN LEE ,  YEONGKWON KO ,  TEAKHOON LEE

IPC: H01L23/498 ,  H01L23/31 ,  H01L23/00 ,  H01L25/18 ,  H01L21/48 ,  H01L25/00 ,  H01L21/56

Abstract: Semiconductor packages may include a semiconductor chip including a chip pad and a lower redistribution that includes a lower redistribution insulating layer and a lower redistribution pattern. The lower redistribution insulating layer may include a top surface facing the semiconductor chip. The semiconductor packages may also include a molding layer on a side of the semiconductor chip and including a bottom surface facing the lower redistribution structure and a conductive post in the molding layer. The conductive post may include a bottom surface contacting the lower redistribution. The top surface of the lower redistribution insulating layer may be closer to a top surface of the conductive post than a top surface of the molding layer. A roughness of the top surface of the molding layer may be greater than a roughness of the top surface of the conductive post.