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    SEMICONDUCTOR PACKAGE AND METHOD OF FABRICATING THE SAME
    1.
    发明申请
    SEMICONDUCTOR PACKAGE AND METHOD OF FABRICATING THE SAME 有权

    公开(公告)号：US20220320043A1

    公开(公告)日：2022-10-06

    申请号：US17529798

    申请日：2021-11-18

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： JAEKYUNG YOO ,  JONGHO LEE ,  YEONGKWON KO

    IPC: H01L25/065 ,  H01L23/00 ,  H01L23/31 ,  H01L23/367 ,  H01L25/00 ,  H01L21/48 ,  H01L21/56 ,  H01L23/498 ,  H01L23/538

    Abstract: A semiconductor package includes a lower substrate including a central region and an edge region, an upper substrate on the central region of the lower substrate, a first semiconductor chip on the upper substrate, a second semiconductor chip on the upper substrate and horizontally spaced apart from the first semiconductor chip, a reinforcing structure on the edge region of the lower substrate, and a molding layer that covers an inner sidewall of the reinforcing structure, a top surface of the lower substrate, a sidewall of the first semiconductor chip, a sidewall of the second semiconductor chip, and the upper substrate. The molding layer is interposed between the lower substrate and the upper substrate, between the upper substrate and the first semiconductor chip, and between the upper substrate and the second semiconductor chip. The first semiconductor chip is of a different type from the second semiconductor chip.

    SEMICONDUCTOR PACKAGE AND METHOD OF MANUFACTURE
    3.
    发明申请
    SEMICONDUCTOR PACKAGE AND METHOD OF MANUFACTURE 有权

    公开(公告)号：US20220093481A1

    公开(公告)日：2022-03-24

    申请号：US17177725

    申请日：2021-02-17

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： JINWOO PARK ,  JONGHO LEE ,  YEONGKWON KO

    IPC: H01L23/31 ,  H01L25/18 ,  H01L23/29 ,  H01L23/498 ,  H01L23/00 ,  H01L25/00 ,  H01L21/56

    Abstract: A method of manufacture for a semiconductor package includes; forming a molding member on side surfaces of the semiconductor chips, using an adhesive to attach a carrier substrate to upper surfaces of the molding member and the semiconductor chips, using a first blade having a first blade-width to cut away selected portions of the carrier substrate and portions of the adhesive underlying the selected portions of the carrier substrate, and using the first blade to partially cut into an upper surface of the molding member to form a first cutting groove, wherein the selected portions of the carrier substrate are dispose above portions of the molding member between adjacent ones of semiconductor chips, using a second blade having a second blade-width narrower than the first blade-width to cut through a lower surface of the molding member to form a second cutting groove, wherein a combination of the first cutting groove and the second cutting groove separate a package structure including a semiconductor chip supported by a cut portion of the carrier substrate and bonding the package structure to an upper surface of a package substrate.

    SEMICONDUCTOR PACKAGE HAVING DUMMY PADS AND METHOD OF MANUFACTURING SEMICONDUCTOR PACKAGE HAVING DUMMY PADS
    4.
    发明申请
    SEMICONDUCTOR PACKAGE HAVING DUMMY PADS AND METHOD OF MANUFACTURING SEMICONDUCTOR PACKAGE HAVING DUMMY PADS 有权

    公开(公告)号：US20210005553A1

    公开(公告)日：2021-01-07

    申请号：US16805890

    申请日：2020-03-02

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： YOUNG KUN JEE ,  HAE-JUNG YU ,  SANGWON KIM ,  UN-BYOUNG KANG ,  JONGHO LEE ,  DAE-WOO KIM ,  WONJAE LEE

    IPC: H01L23/538 ,  H01L23/498 ,  H01L25/18

    Abstract: A semiconductor package includes a package substrate, a plurality of package terminals disposed on the bottom surface of the package substrate, and an interposer substrate disposed on the top surface of the package substrate, a plurality of interposer terminals disposed on the bottom surface of the interposer substrate and electrically connected to the package substrate, a first semiconductor chip disposed on the top surface of the interposer substrate, a second semiconductor chip disposed on the top surface of the interposer substrate and disposed to be horizontally separated from the first semiconductor chip, a first plurality of signal pads disposed on the top surface of the interposer substrate and electrically connected to wiring in the interposer substrate and one or more circuits in the first semiconductor chip, a second plurality of signal pads disposed on the top surface of the interposer substrate and electrically connected to wiring in the interposer substrate and to one or more circuits in the second semiconductor chip, and a plurality of dummy pads disposed outside of an area occupied by the first semiconductor chip or the second semiconductor chip from a top-down view and disposed on the top surface of the interposer substrate. Each pad of the first plurality of signal pads and the second plurality of signal pads is configured to transfer signals between the interposer substrate and a respective semiconductor chip, and each pad of the dummy pads is not configured to transfer signals between the interposer substrate and any semiconductor chip disposed thereon.

    SEMICONDUCTOR PACKAGE WITH INCREASED THERMAL RADIATION EFFICIENCY
    5.
    发明申请
    SEMICONDUCTOR PACKAGE WITH INCREASED THERMAL RADIATION EFFICIENCY 有权

    公开(公告)号：US20240429205A1

    公开(公告)日：2024-12-26

    申请号：US18826592

    申请日：2024-09-06

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： SANG-SICK PARK ,  UN-BYOUNG KANG ,  JONGHO LEE ,  TEAK HOON LEE

    IPC: H01L25/065 ,  H01L23/00

    Abstract: Disclosed is a semiconductor package with increased thermal radiation efficiency, which includes: a first die having signal and dummy regions and including first vias in the signal region, a second die on the first die and including second vias in the signal region, first die pads on a top surface of the first die and coupled to the first vias, first connection terminals on the first die pads which couple the second vias to the first vias, second die pads in the dummy region and on the top surface of the first die, and second connection terminals on the second die pads and electrically insulated from the first vias and the second vias. Each of the second die pads has a rectangular planar shape whose major axis is provided along a direction that leads away from the signal region.

    SEMICONDUCTOR PACKAGE HAVING DUMMY PADS AND METHOD OF MANUFACTURING SEMICONDUCTOR PACKAGE HAVING DUMMY PADS
    6.
    发明申请
    SEMICONDUCTOR PACKAGE HAVING DUMMY PADS AND METHOD OF MANUFACTURING SEMICONDUCTOR PACKAGE HAVING DUMMY PADS 有权

    公开(公告)号：US20220173044A1

    公开(公告)日：2022-06-02

    申请号：US17674900

    申请日：2022-02-18

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： YOUNG KUN JEE ,  HAE-JUNG YU ,  SANGWON KIM ,  UN-BYOUNG KANG ,  JONGHO LEE ,  DAE-WOO KIM ,  WONJAE LEE

    IPC: H01L23/538 ,  H01L25/18 ,  H01L23/498

    Abstract: A semiconductor package includes a package substrate, a plurality of package terminals disposed on the bottom surface of the package substrate, and an interposer substrate disposed on the top surface of the package substrate, a plurality of interposer terminals disposed on the bottom surface of the interposer substrate and electrically connected to the package substrate, a first semiconductor chip disposed on the top surface of the interposer substrate, a second semiconductor chip disposed on the top surface of the interposer substrate and disposed to be horizontally separated from the first semiconductor chip, a first plurality of signal pads disposed on the top surface of the interposer substrate and electrically connected to wiring in the interposer substrate and one or more circuits in the first semiconductor chip, a second plurality of signal pads disposed on the top surface of the interposer substrate and electrically connected to wiring in the interposer substrate and to one or more circuits in the second semiconductor chip, and a plurality of dummy pads disposed outside of an area occupied by the first semiconductor chip or the second semiconductor chip from a top-down view and disposed on the top surface of the interposer substrate. Each pad of the first plurality of signal pads and the second plurality of signal pads is configured to transfer signals between the interposer substrate and a respective semiconductor chip, and each pad of the dummy pads is not configured to transfer signals between the interposer substrate and any semiconductor chip disposed thereon.

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