公开(公告)号：US20220102528A1

公开(公告)日：2022-03-31

申请号：US17339144

申请日：2021-06-04

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jin A. KIM ,  Ho-In RYU ,  Jae Won NA

IPC: H01L29/66 ,  H01L29/06 ,  H01L29/423

Abstract: A semiconductor device includes a substrate having a trench, a conductive pattern in the trench, a spacer structure on a side surface of the conductive pattern, and a buried contact including a first portion apart from the conductive pattern by the spacer structure and filling a contact recess, and a second portion on the first portion having a pillar shape with a width smaller than that of a top surface of the first portion. The spacer structure includes a first spacer extending along the second portion of the buried contact on the first portion of the buried contact and contacting the buried contact, a second spacer extending along the first spacer, and a third spacer extending along the side surface of the conductive pattern and the trench and apart from the first spacer by the second spacer, the first spacer includes silicon oxide, and the second spacer includes silicon nitride.

公开(公告)号：US20250016987A1

公开(公告)日：2025-01-09

申请号：US18396289

申请日：2023-12-26

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jae Won NA ,  Jul Pin PARK ,  Jong Moo LEE ,  Chang Sik KIM

IPC: H10B12/00

Abstract: A semiconductor memory device including a bit line including a metal and extending in a first direction on a substrate; a channel structure on the bit line, including a first channel pattern extending in a second direction, and a second channel pattern spaced apart from the first channel pattern in the first direction and extending in the second direction; a liner film between the bit line and the channel structure, and including the metal; a first word line between the first and second channel patterns, and the first word line extending in the second direction; a second word line between the first and second channel patterns, and extending in the second direction, and the second word line spaced apart from the first word line in the first direction; and first and second capacitors respectively on the first and second channel patterns, and connected to the first and second channel patterns.

公开(公告)号：US20240155829A1

公开(公告)日：2024-05-09

申请号：US18339861

申请日：2023-06-22

Applicant: Samsung Electronics Co., Ltd.

Inventor： Changsik KIM ,  Jae Won NA ,  Junhwa SONG ,  Dong-Sik PARK

IPC: H10B12/00 ,  H01L23/00 ,  H01L25/065 ,  H01L25/18 ,  H10B80/00

CPC classification number: H10B12/315 ,  H01L24/08 ,  H01L25/0657 ,  H01L25/18 ,  H10B12/50 ,  H10B80/00 ,  H01L2224/08145 ,  H01L2924/1431 ,  H01L2924/1436

Abstract: A semiconductor memory device may include a plurality of bit lines extending in a first direction on a substrate, a plurality of active pillars respectively on the bit lines, a word line extending in a second direction along the plurality of active pillars, a plurality of landing pads respectively on the plurality of active pillars, and a plurality of data storage patterns respectively on the plurality of landing pads. Each of the plurality of active pillars may have a length extending in a direction perpendicular to an upper surface of the substrate. The word line has a wavy shape when viewed in a plan view.

公开(公告)号：US20240114674A1

公开(公告)日：2024-04-04

申请号：US18212422

申请日：2023-06-21

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jae Won NA ,  Chang Sik KIM ,  Jun Hwa SONG ,  Ji Hee JUN

IPC: H10B12/00

CPC classification number: H10B12/315 ,  H10B12/05

Abstract: A semiconductor memory device includes a substrate; a bit-line on the substrate and extending in a first direction; first and second channel patterns on the bit-line; the second channel pattern being spaced apart from the first channel pattern in the first direction; a first word-line between the first and second channel patterns and extending in a second direction that intersects the first direction; a second word-line between the first and second channel patterns, extending in the second direction, and being spaced apart from the first word-line in the first direction; capacitors on and connected to the channel patterns; wherein the first and second channel patterns include first and second metal oxide patterns sequentially on the bit-line, each of the first and second metal oxide patterns include an amorphous metal oxide, and a composition of the first metal oxide pattern is different from a composition of the second metal oxide pattern.