中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

11 records (took 0.014 seconds)

    SEMICONDUCTOR MEMORY DEVICES AND METHODS FOR FABRICATING THE SAME
    3.
    发明申请
    SEMICONDUCTOR MEMORY DEVICES AND METHODS FOR FABRICATING THE SAME 有权

    公开(公告)号：US20220139927A1

    公开(公告)日：2022-05-05

    申请号：US17371873

    申请日：2021-07-09

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Ji Hoon CHANG ,  Jung-Hoon HAN ,  Ji Seok HONG ,  Dong-Sik PARK

    IPC: H01L27/108 ,  H01L29/66

    Abstract: The present disclosure provides a semiconductor memory device capable of improving reliability and performance. The semiconductor memory device comprises a substrate including a cell region and a peripheral region around the cell region, a cell region isolation film which defines the cell region, a bit line structure in the cell region, a first peripheral gate structure on the peripheral region of the substrate, the first peripheral gate structure comprising a first peripheral gate conduction film and a first peripheral capping film on the first peripheral gate conduction film, a peripheral interlayer insulating film around the first peripheral gate structure and an insertion interlayer insulating film on the peripheral interlayer insulating film and the first peripheral gate structure, and including a material different from the peripheral interlayer insulating film. An upper face of the peripheral interlayer insulating film is lower than an upper face of the first peripheral capping film.

    SEMICONDUCTOR DEVICES HAVING THROUGH ELECTRODES AND METHODS FOR FABRICATING THE SAME
    4.
    发明申请
    SEMICONDUCTOR DEVICES HAVING THROUGH ELECTRODES AND METHODS FOR FABRICATING THE SAME 有权

    公开(公告)号：US20210143086A1

    公开(公告)日：2021-05-13

    申请号：US17152012

    申请日：2021-01-19

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Dong-Wan KIM ,  Jung-Hoon HAN ,  Dong-Sik PARK

    IPC: H01L23/48 ,  H01L23/538 ,  H01L21/768

    Abstract: The semiconductor device includes a substrate including an integrated circuit and a contact that are electrically connected to each other, an insulation layer covering the substrate and including metal lines, and a through electrode electrically connected to the integrated circuit. The insulation layer includes an interlayer dielectric layer on the substrate and an intermetal dielectric layer on the interlayer dielectric layer. The metal lines include a first metal line in the interlayer dielectric layer and electrically connected to the contact, and a plurality of second metal lines in the intermetal dielectric layer and electrically connected to the first metal line and the through electrode. The through electrode includes a top surface higher than a top surface of the contact.

    SEMICONDUCTOR MEMORY DEVICE
    5.
    发明公开
    SEMICONDUCTOR MEMORY DEVICE 审中-公开

    公开(公告)号：US20240138142A1

    公开(公告)日：2024-04-25

    申请号：US18220861

    申请日：2023-07-11

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Jul Pin PARK ,  Jae Joon SONG ,  Heon Jun HA ,  Dong-Sik PARK

    IPC: H10B12/00 ,  H01L23/528

    CPC classification number: H10B12/482 ,  H01L23/5283 ,  H10B12/315 ,  H10B12/485 ,  H10B12/488 ,  H10B12/50

    Abstract: Disclosed is a semiconductor memory device including a peripheral gate structure on a substrate, bitlines disposed on the peripheral gate structure and extending in a first direction, a protruding insulating pattern including channel trenches, extending in a second direction intersecting the first direction, channel structures disposed on the bitlines in the channel trenches and including a metal oxide, first wordlines disposed on the channel structures and extending in the second direction, second wordlines disposed on the channel structures, extending in the second direction, and spaced apart from the first wordlines in the first direction, landing pads disposed on the channel structures and connected to the channel structures, pad separation patterns disposed on the protruding insulating pattern and separating the landing pads, first passage patterns connected to the protruding insulating pattern through pad separation patterns and formed of an oxide-based insulating material, and data storage patterns disposed on the landing pads.

    SEMICONDUCTOR DEVICE
    6.
    发明公开
    SEMICONDUCTOR DEVICE 审中-公开

    公开(公告)号：US20230189510A1

    公开(公告)日：2023-06-15

    申请号：US17854130

    申请日：2022-06-30

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Jihoon CHANG ,  Dong-Wan KIM ,  Dong-Sik PARK

    IPC: H01L27/108

    CPC classification number: H01L27/10897 ,  H01L27/10814 ,  H01L27/10823

    Abstract: A semiconductor device includes a substrate having an active cell region and an interfacial region adjacent to each other in a first direction, bit lines on the active cell region of the substrate that are spaced apart from each other in a second direction that intersects the first direction, and bit-line pads on the interfacial region of the substrate that are spaced apart from each other in the second direction. Each of the bit lines includes a first bit line and a second bit line that extend in the first direction and are spaced apart from each other in the second direction, a connection part that connects a first end of the first bit line to a second end of the second bit line, and a coupling part that connects one of the bit-line pads to one of the first bit line, the second bit line, and the connection part.

    SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME
    7.
    发明申请
    SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME 有权

    公开(公告)号：US20230039149A1

    公开(公告)日：2023-02-09

    申请号：US17747423

    申请日：2022-05-18

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Dong-Wan KIM ,  Keonhee PARK ,  Dong-Sik PARK ,  Joonsuk PARK ,  Jihoon CHANG ,  Hyeon-Woo JANG

    IPC: H01L27/108 ,  H01L21/3213

    Abstract: Disclosed are semiconductor devices and their fabrication methods. The semiconductor device comprises a substrate including a peripheral block and cell blocks each including a cell center region, a cell edge region, and a cell middle region, and bit lines extending on each cell block in a first direction. The bit lines include center bit lines, middle bit lines, and edge bit lines. The bit line has first and second lateral surfaces opposite to each other in a second direction. The first lateral surface straightly extends along the first direction on the cell center region, the cell middle region, and the cell edge region. The second lateral surface straightly extends along the first direction on the cell center region and the cell edge region, and the second lateral surface extends along a third direction, that intersects the first direction and the second direction, on the cell middle region.

    SEMICONDUCTOR MEMORY DEVICE
    8.
    发明公开
    SEMICONDUCTOR MEMORY DEVICE 审中-公开

    公开(公告)号：US20240237333A9

    公开(公告)日：2024-07-11

    申请号：US18220861

    申请日：2023-07-12

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Jul Pin PARK ,  Jae Joon SONG ,  Heon Jun HA ,  Dong-Sik PARK

    IPC: H10B12/00 ,  H01L23/528

    CPC classification number: H10B12/482 ,  H01L23/5283 ,  H10B12/315 ,  H10B12/485 ,  H10B12/488 ,  H10B12/50

    Abstract: Disclosed is a semiconductor memory device including a peripheral gate structure on a substrate, bitlines disposed on the peripheral gate structure and extending in a first direction, a protruding insulating pattern including channel trenches, extending in a second direction intersecting the first direction, channel structures disposed on the bitlines in the channel trenches and including a metal oxide, first wordlines disposed on the channel structures and extending in the second direction, second wordlines disposed on the channel structures, extending in the second direction, and spaced apart from the first wordlines in the first direction, landing pads disposed on the channel structures and connected to the channel structures, pad separation patterns disposed on the protruding insulating pattern and separating the landing pads, first passage patterns connected to the protruding insulating pattern through pad separation patterns and formed of an oxide-based insulating material, and data storage patterns disposed on the landing pads.

    SEMICONDUCTOR MEMORY DEVICE
    10.
    发明公开
    SEMICONDUCTOR MEMORY DEVICE 审中-公开

    公开(公告)号：US20230189504A1

    公开(公告)日：2023-06-15

    申请号：US17953401

    申请日：2022-09-27

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Keon Hee PARK ,  Soo Ho SHIN ,  Hyeon-Woo JANG ,  Dong-Sik PARK ,  Ga Eun LEE

    IPC: H01L27/108

    CPC classification number: H01L27/10814 ,  H01L27/10823

    Abstract: A semiconductor memory device includes a landing pad on a substrate, a lower electrode on and connected to the landing pad, a dielectric layer on and extending along a profile of the lower electrode, an upper electrode on the dielectric layer, and an upper plate electrode on the upper electrode, the upper plate electrode including a first sub-plate electrode and a second sub-plate electrode doped with boron, a first concentration of the boron in the first sub-plate electrode being greater than a second concentration of the boron in the second sub-plate electrode.

Patent Agency Ranking