公开(公告)号：US20220085028A1

公开(公告)日：2022-03-17

申请号：US17332307

申请日：2021-05-27

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jin A KIM ,  Ho-In RYU ,  Kyo-Suk CHAE ,  Joon Yong CHOE

IPC: H01L27/108

Abstract: A semiconductor device may include a substrate including trenches and contact recesses having a curved surface profile, conductive patterns in the trenches, buried contacts including first portions filling the contact recesses and second portions on the first portions, and spacer structures including first and second spacers. The second portions may have a pillar shape and a smaller width than top surfaces of the first portions. The buried contacts may be spaced apart from the conductive patterns by the spacer structures. The first spacers may be on the first portions of the buried contacts at outermost parts of the spacer structures. The first spacers may extend along the second portions of the buried contacts and contact the buried contacts. The second spacers may extend along the side surfaces of the conductive patterns and the trenches. The second spacers may contact the conductive patterns. The first spacers may include silicon oxide.

公开(公告)号：US20200312852A1

公开(公告)日：2020-10-01

申请号：US16902338

申请日：2020-06-16

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Ho-In RYU ,  Taiheui CHO ,  Keunnam KIM ,  Kyehee YEOM ,  Junghwan PARK ,  Hyeon-Woo JANG

IPC: H01L27/105 ,  H01L27/108 ,  H01L29/423

Abstract: A semiconductor device includes a substrate including a cell region and a peripheral region, a cell gate electrode buried in a groove crossing a cell active portion of the cell region, a cell line pattern crossing over the cell gate electrode, the cell line pattern being connected to a first source/drain region in the cell active portion at a side of the cell gate electrode, a peripheral gate pattern crossing over a peripheral active portion of the peripheral region, a planarized interlayer insulating layer on the substrate around the peripheral gate pattern, and a capping insulating layer on the planarized interlayer insulating layer and a top surface of the peripheral gate pattern, the capping insulating layer including an insulating material having an etch selectivity with respect to the planarized interlayer insulating layer.

公开(公告)号：US20190363088A1

公开(公告)日：2019-11-28

申请号：US16532857

申请日：2019-08-06

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Ho-In RYU ,  Taiheui CHO ,  Keunnam KIM ,  Kyehee YEOM ,  Junghwan PARK ,  Hyeon-Woo JANG

IPC: H01L27/105 ,  H01L27/108 ,  H01L29/423

Abstract: A semiconductor device includes a substrate including a cell region and a peripheral region, a cell gate electrode buried in a groove crossing a cell active portion of the cell region, a cell line pattern crossing over the cell gate electrode, the cell line pattern being connected to a first source/drain region in the cell active portion at a side of the cell gate electrode, a peripheral gate pattern crossing over a peripheral active portion of the peripheral region, a planarized interlayer insulating layer on the substrate around the peripheral gate pattern, and a capping insulating layer on the planarized interlayer insulating layer and a top surface of the peripheral gate pattern, the capping insulating layer including an insulating material having an etch selectivity with respect to the planarized interlayer insulating layer.

公开(公告)号：US20140154882A1

公开(公告)日：2014-06-05

申请号：US14097786

申请日：2013-12-05

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Dae-Ik KIM ,  Ho-In RYU ,  Nak-Jin SON ,  Yoo-Sang HWANG

IPC: H01L27/108

CPC classification number: H01L27/10855 ,  H01L27/10876 ,  H01L27/10885 ,  H01L27/10888

Abstract: A method for fabricating a semiconductor device includes forming a device isolation layer pattern on a substrate to form an active region, the active region including a first contact forming region at a center p of the active region and second and third contact forming regions at edges of the active region, forming an insulating layer and a first conductive layer on the substrate, forming a mask pattern having an isolated shape on the first conductive layer, etching the first conductive layer and the insulating layer to expose the active region of the first contact forming region by using the mask pattern, to form an opening portion between pillar structures, forming a second conductive layer in the opening, and patterning the second conductive layer and the first preliminary conductive layer pattern to form a wiring structure contacting the first contact forming region and having an extended line shape.

Abstract translation: 一种用于制造半导体器件的方法包括在衬底上形成器件隔离层图案以形成有源区，所述有源区包括位于有源区的中心p处的第一接触形成区和第二接触形成区 所述有源区，在所述基板上形成绝缘层和第一导电层，在所述第一导电层上形成具有隔离形状的掩模图案，蚀刻所述第一导电层和所述绝缘层，以暴露所述第一触点形成的有源区 通过使用掩模图案形成柱状结构之间的开口部分，在开口中形成第二导电层，图案化第二导电层和第一预导电层图案，以形成与第一接触形成区域接触的布线结构和 具有延长的线形。

公开(公告)号：US20220102528A1

公开(公告)日：2022-03-31

申请号：US17339144

申请日：2021-06-04

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jin A. KIM ,  Ho-In RYU ,  Jae Won NA

IPC: H01L29/66 ,  H01L29/06 ,  H01L29/423

Abstract: A semiconductor device includes a substrate having a trench, a conductive pattern in the trench, a spacer structure on a side surface of the conductive pattern, and a buried contact including a first portion apart from the conductive pattern by the spacer structure and filling a contact recess, and a second portion on the first portion having a pillar shape with a width smaller than that of a top surface of the first portion. The spacer structure includes a first spacer extending along the second portion of the buried contact on the first portion of the buried contact and contacting the buried contact, a second spacer extending along the first spacer, and a third spacer extending along the side surface of the conductive pattern and the trench and apart from the first spacer by the second spacer, the first spacer includes silicon oxide, and the second spacer includes silicon nitride.

公开(公告)号：US20220102353A1

公开(公告)日：2022-03-31

申请号：US17339130

申请日：2021-06-04

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jin A. KIM ,  Ho-In RYU ,  Seong Min PARK

IPC: H01L27/108 ,  H01L23/532 ,  H01L21/768

Abstract: A semiconductor device includes a semiconductor substrate including a trench, a direct contact in the trench, the direct contact having a width smaller than a width of the trench, a bit line structure on the direct contact, the bit line structure having a width smaller than the width of the trench, a first spacer including a first portion and a second portion, the first portion extending along an entire side surface of the direct contact, and the second portion extending along the trench, a second spacer on the first spacer, the second spacer filling the trench, a third spacer on the second spacer, and an air spacer on the third spacer, the air spacer being spaced apart from the second spacer by the third spacer, wherein the first spacer includes silicon oxide.

公开(公告)号：US20180233506A1

公开(公告)日：2018-08-16

申请号：US15954744

申请日：2018-04-17

Applicant: Samsung Electronics Co., Ltd.

Inventor： Chan-Sic YOON ,  Ho-In RYU ,  Ki-Seok LEE ,  Chang-Hyun CHO

IPC: H01L27/108 ,  H01L29/423 ,  H01L21/311 ,  H01L21/761

CPC classification number: H01L27/10876 ,  H01L21/31111 ,  H01L21/761 ,  H01L27/10814 ,  H01L27/10855 ,  H01L27/10891 ,  H01L29/4236

Abstract: A semiconductor device includes a substrate having an active region defined by a device isolation layer and at least a gate trench linearly extending in a first direction to cross the active region, the active region having a gate area at a bottom of the gate trench and a junction area at a surface of the substrate. The device further may include a first conductive line filling the gate trench and extending in the first direction, the first conductive line having a buried gate structure on the gate area of the active region. The device also may include a junction including implanted dopants at the junction area of the active region, and a junction separator on the device isolation layer and defining the junction. The junction separator may be formed of an insulative material and have an etch resistance greater than that of the device isolation layer.