公开(公告)号：US20220165887A1

公开(公告)日：2022-05-26

申请号：US17370464

申请日：2021-07-08

Applicant: Samsung Electronics Co., Ltd.

Inventor： Seungmin SONG ,  Taeyong KWON ,  Jaehyeoung MA ,  Namhyun LEE

IPC: H01L29/786 ,  H01L27/092 ,  H01L29/06 ,  H01L29/417 ,  H01L29/423 ,  H01L21/02 ,  H01L21/8238 ,  H01L29/66

Abstract: A semiconductor device including a substrate including a division region extending in a first direction, first and second active patterns on the substrate with the division region interposed therebetween, the first and the second active patterns being spaced apart from each other in a second direction perpendicular to the first direction, gate electrodes extending in the first direction and crossing the first and second active patterns, a first channel pattern on the first active pattern, and a second channel pattern on the second active pattern may be provided. The smallest width of the first active pattern may be smaller than the smallest width of the second active pattern, in the first direction. An end portion of the first channel pattern adjacent to the division region may include a protruding portion extending in the first direction, and the protruding portion may have a triangle shape in a plan view.

公开(公告)号：US20240030355A1

公开(公告)日：2024-01-25

申请号：US18478410

申请日：2023-09-29

Applicant: Samsung Electronics Co., Ltd.

Inventor： Seungmin SONG ,  Taeyong KWON ,  Jaehyeoung MA ,  Namhyun LEE

IPC: H01L29/786 ,  H01L27/092 ,  H01L29/06 ,  H01L29/417 ,  H01L29/423 ,  H01L29/66 ,  H01L21/8238 ,  H01L21/02

CPC classification number: H01L29/78696 ,  H01L27/092 ,  H01L29/0665 ,  H01L29/41733 ,  H01L29/42392 ,  H01L29/78618 ,  H01L29/66742 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823864 ,  H01L21/823871 ,  H01L29/66545 ,  H01L29/66553 ,  H01L21/0259

Abstract: A semiconductor device including a substrate including a division region extending in a first direction, first and second active patterns on the substrate with the division region interposed therebetween, the first and the second active patterns being spaced apart from each other in a second direction perpendicular to the first direction, gate electrodes extending in the first direction and crossing the first and second active patterns, a first channel pattern on the first active pattern, and a second channel pattern on the second active pattern may be provided. The smallest width of the first active pattern may be smaller than the smallest width of the second active pattern, in the first direction. An end portion of the first channel pattern adjacent to the division region may include a protruding portion extending in the first direction, and the protruding portion may have a triangle shape in a plan view.

公开(公告)号：US20230087731A1

公开(公告)日：2023-03-23

申请号：US17994565

申请日：2022-11-28

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Junggun YOU ,  Joohee JUNG ,  Jaehyeoung MA ,  Namhyun LEE

IPC: H01L29/78 ,  H01L29/10 ,  H01L27/088 ,  H01L29/06 ,  H01L29/423

Abstract: A semiconductor device including a substrate having a central region and a peripheral region; an integrated circuit structure on the central region; and a first structure on the peripheral region and surrounding the central region, wherein a portion of the first structure includes a first fin structure defined by a device isolation region in the substrate; a first dielectric layer covering an upper surface and side surfaces of the first fin structure and an upper surface of the device isolation region; a first gate structure on the first fin structure, the first gate structure including a first gate conductive layer, a first gate dielectric layer covering lower and side surfaces of the first gate conductive layer, and first gate spacer layers on side walls of the first gate conductive layer; and a first insulating structure covering the first dielectric layer and the first gate structure.

公开(公告)号：US20240413252A1

公开(公告)日：2024-12-12

申请号：US18812404

申请日：2024-08-22

Applicant: Samsung Electronics Co., Ltd.

Inventor： Seungmin SONG ,  Taeyong KWON ,  Jaehyeoung MA ,  Namhyun LEE

IPC: H01L29/786 ,  H01L21/02 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/06 ,  H01L29/417 ,  H01L29/423 ,  H01L29/66

Abstract: A semiconductor device including a substrate including a division region extending in a first direction, first and second active patterns on the substrate with the division region interposed therebetween, the first and the second active patterns being spaced apart from each other in a second direction perpendicular to the first direction, gate electrodes extending in the first direction and crossing the first and second active patterns, a first channel pattern on the first active pattern, and a second channel pattern on the second active pattern may be provided. The smallest width of the first active pattern may be smaller than the smallest width of the second active pattern, in the first direction. An end portion of the first channel pattern adjacent to the division region may include a protruding portion extending in the first direction, and the protruding portion may have a triangle shape in a plan view.

公开(公告)号：US20220037521A1

公开(公告)日：2022-02-03

申请号：US17205282

申请日：2021-03-18

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Junggun YOU ,  Joohee JUNG ,  Jaehyeoung MA ,  Namhyun LEE

IPC: H01L29/78 ,  H01L29/10 ,  H01L29/423 ,  H01L27/088 ,  H01L29/06

Abstract: A semiconductor device including a substrate having a central region and a peripheral region; an integrated circuit structure on the central region; and a first structure on the peripheral region and surrounding the central region, wherein a portion of the first structure includes a first fin structure defined by a device isolation region in the substrate; a first dielectric layer covering an upper surface and side surfaces of the first fin structure and an upper surface of the device isolation region; a first gate structure on the first fin structure, the first gate structure including a first gate conductive layer, a first gate dielectric layer covering lower and side surfaces of the first gate conductive layer, and first gate spacer layers on side walls of the first gate conductive layer; and a first insulating structure covering the first dielectric layer and the first gate structure.