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公开(公告)号:US20220189970A1
公开(公告)日:2022-06-16
申请号:US17392377
申请日:2021-08-03
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor: Haegeon JUNG , Taeyong KWON , Kwang-Yong YANG , Youngmook OH , Bokyoung LEE , Seung Mo HA , Hyunggoo LEE
IPC: H01L27/11 , H01L27/088 , H01L29/417 , H01L29/78 , H01L29/66 , H01L29/06
Abstract: A semiconductor device includes a substrate having a first memory cell and a second memory cell, the first and second memory cells being adjacent to each other in a first direction, first to fourth memory fins adjacent to each other in the first direction in the first memory cell, the first to fourth memory fins protruding from the substrate, fifth to eighth memory fins adjacent to each other in the first direction in the second memory cell, the fifth to eighth memory fins protruding from the substrate, and a first shallow device isolation layer between the fourth memory fin and the fifth memory fin, a sidewall of the first shallow device isolation layer having an inflection point.
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公开(公告)号:US20240413252A1
公开(公告)日:2024-12-12
申请号:US18812404
申请日:2024-08-22
Applicant: Samsung Electronics Co., Ltd.
Inventor: Seungmin SONG , Taeyong KWON , Jaehyeoung MA , Namhyun LEE
IPC: H01L29/786 , H01L21/02 , H01L21/8238 , H01L27/092 , H01L29/06 , H01L29/417 , H01L29/423 , H01L29/66
Abstract: A semiconductor device including a substrate including a division region extending in a first direction, first and second active patterns on the substrate with the division region interposed therebetween, the first and the second active patterns being spaced apart from each other in a second direction perpendicular to the first direction, gate electrodes extending in the first direction and crossing the first and second active patterns, a first channel pattern on the first active pattern, and a second channel pattern on the second active pattern may be provided. The smallest width of the first active pattern may be smaller than the smallest width of the second active pattern, in the first direction. An end portion of the first channel pattern adjacent to the division region may include a protruding portion extending in the first direction, and the protruding portion may have a triangle shape in a plan view.
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公开(公告)号:US20240030355A1
公开(公告)日:2024-01-25
申请号:US18478410
申请日:2023-09-29
Applicant: Samsung Electronics Co., Ltd.
Inventor: Seungmin SONG , Taeyong KWON , Jaehyeoung MA , Namhyun LEE
IPC: H01L29/786 , H01L27/092 , H01L29/06 , H01L29/417 , H01L29/423 , H01L29/66 , H01L21/8238 , H01L21/02
CPC classification number: H01L29/78696 , H01L27/092 , H01L29/0665 , H01L29/41733 , H01L29/42392 , H01L29/78618 , H01L29/66742 , H01L21/823807 , H01L21/823814 , H01L21/823864 , H01L21/823871 , H01L29/66545 , H01L29/66553 , H01L21/0259
Abstract: A semiconductor device including a substrate including a division region extending in a first direction, first and second active patterns on the substrate with the division region interposed therebetween, the first and the second active patterns being spaced apart from each other in a second direction perpendicular to the first direction, gate electrodes extending in the first direction and crossing the first and second active patterns, a first channel pattern on the first active pattern, and a second channel pattern on the second active pattern may be provided. The smallest width of the first active pattern may be smaller than the smallest width of the second active pattern, in the first direction. An end portion of the first channel pattern adjacent to the division region may include a protruding portion extending in the first direction, and the protruding portion may have a triangle shape in a plan view.
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公开(公告)号:US20230402307A1
公开(公告)日:2023-12-14
申请号:US18133242
申请日:2023-04-11
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor: Taeyong KWON , Yoonjoong KIM , Youngjin YANG , Dain JANG
IPC: H01L21/68 , H01L21/768 , H01L21/02 , H01L23/544 , H01L21/8234
CPC classification number: H01L21/68 , H01L21/76816 , H01L21/02381 , H01L23/544 , H01L21/02576 , H01L21/02579 , H01L21/823487
Abstract: A semiconductor device includes a substrate including a main chip region and a scribe lane region, wherein first trenches are formed in the scribe lane region. A well region doped with impurities is provided on an upper part of the main chip region of the substrate. Align key patterns formed on surfaces of the first trenches and on surfaces of the substrate adjacent to the first trenches in the scribe lane region and having an alternately and repeatedly stacked structure of a silicon germanium pattern and a silicon pattern, are provided. A multi-bridge channel transistor is formed on the main chip region of the substrate.
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公开(公告)号:US20250107150A1
公开(公告)日:2025-03-27
申请号:US18650292
申请日:2024-04-30
Applicant: Samsung Electronics Co., Ltd.
Inventor: Daesik KIM , Seonbae KIM , Taeyong KWON , Changhee KIM , Doohyun LEE , Jaehyun KANG , Jinyoung PARK , Hyunho PARK , Jimin YU , Jinwook LEE , Seunghyun HWANG
IPC: H01L29/417 , H01L21/285 , H01L29/06 , H01L29/08 , H01L29/40 , H01L29/423 , H01L29/45 , H01L29/66 , H01L29/775
Abstract: A semiconductor device includes a substrate including an active region, a gate structure on the substrate, a plurality of channel layers on the active region, spaced apart from each other and surrounded by the gate structure, a source/drain region in a region at which the active region is recessed, on at least one side of the gate structure, and connected to the channel layers, and a contact plug partially recessing the source/drain region from an upper surface of the source/drain region, electrically connected to the source/drain region, and including a metal-semiconductor compound layer along a recessed surface of the source/drain region and a contact conductor layer on the metal-semiconductor compound layer, wherein the metal-semiconductor compound layer has a first thickness on a side surface of the contact conductive layer and a second thickness on a bottom surface of the contact plug, the second thickness being smaller than the first thickness.
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公开(公告)号:US20220165887A1
公开(公告)日:2022-05-26
申请号:US17370464
申请日:2021-07-08
Applicant: Samsung Electronics Co., Ltd.
Inventor: Seungmin SONG , Taeyong KWON , Jaehyeoung MA , Namhyun LEE
IPC: H01L29/786 , H01L27/092 , H01L29/06 , H01L29/417 , H01L29/423 , H01L21/02 , H01L21/8238 , H01L29/66
Abstract: A semiconductor device including a substrate including a division region extending in a first direction, first and second active patterns on the substrate with the division region interposed therebetween, the first and the second active patterns being spaced apart from each other in a second direction perpendicular to the first direction, gate electrodes extending in the first direction and crossing the first and second active patterns, a first channel pattern on the first active pattern, and a second channel pattern on the second active pattern may be provided. The smallest width of the first active pattern may be smaller than the smallest width of the second active pattern, in the first direction. An end portion of the first channel pattern adjacent to the division region may include a protruding portion extending in the first direction, and the protruding portion may have a triangle shape in a plan view.
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