公开(公告)号：US20240030355A1

公开(公告)日：2024-01-25

申请号：US18478410

申请日：2023-09-29

Applicant: Samsung Electronics Co., Ltd.

Inventor： Seungmin SONG ,  Taeyong KWON ,  Jaehyeoung MA ,  Namhyun LEE

IPC: H01L29/786 ,  H01L27/092 ,  H01L29/06 ,  H01L29/417 ,  H01L29/423 ,  H01L29/66 ,  H01L21/8238 ,  H01L21/02

CPC classification number: H01L29/78696 ,  H01L27/092 ,  H01L29/0665 ,  H01L29/41733 ,  H01L29/42392 ,  H01L29/78618 ,  H01L29/66742 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823864 ,  H01L21/823871 ,  H01L29/66545 ,  H01L29/66553 ,  H01L21/0259

Abstract: A semiconductor device including a substrate including a division region extending in a first direction, first and second active patterns on the substrate with the division region interposed therebetween, the first and the second active patterns being spaced apart from each other in a second direction perpendicular to the first direction, gate electrodes extending in the first direction and crossing the first and second active patterns, a first channel pattern on the first active pattern, and a second channel pattern on the second active pattern may be provided. The smallest width of the first active pattern may be smaller than the smallest width of the second active pattern, in the first direction. An end portion of the first channel pattern adjacent to the division region may include a protruding portion extending in the first direction, and the protruding portion may have a triangle shape in a plan view.

公开(公告)号：US20240038843A1

公开(公告)日：2024-02-01

申请号：US18378710

申请日：2023-10-11

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Soojin JEONG ,  Sunwook KIM ,  Junbeom PARK ,  Seungmin SONG

IPC: H01L29/08 ,  H01L27/088 ,  H01L29/16 ,  H01L29/78

CPC classification number: H01L29/0847 ,  H01L27/0886 ,  H01L29/1608 ,  H01L29/7854

Abstract: A semiconductor device includes an active pattern on a substrate, the active pattern extending in a first direction parallel to an upper surface of the substrate, a gate structure on the active pattern, the gate structure extending in a second direction parallel to the upper surface of the substrate and crossing the first direction, channels spaced apart from each other in a third direction perpendicular to the upper surface of the substrate, each of the channels extending through the gate structure, a source/drain layer on a portion of the active pattern adjacent the gate structure, the source/drain layer contacting the channels, and a sacrificial pattern on an upper surface of each of opposite edges of the portion of the active pattern in the second direction, the sacrificial pattern contacting a lower portion of a sidewall of the source/drain layer and including silicon-germanium.

公开(公告)号：US20240030314A1

公开(公告)日：2024-01-25

申请号：US18175176

申请日：2023-02-27

Applicant: Samsung Electronics Co., Ltd.

Inventor： Seungmin SONG ,  Bongsoo Kim ,  Soojin Jeong

IPC: H01L29/66 ,  H01L29/40 ,  H01L21/311 ,  H01L21/3115 ,  H01L29/08 ,  H01L21/02 ,  H01L29/423

CPC classification number: H01L29/6656 ,  H01L29/401 ,  H01L21/311 ,  H01L21/31155 ,  H01L29/0847 ,  H01L21/02107 ,  H01L29/42364

Abstract: A semiconductor device includes a substrate including an active pattern, a pair of channel patterns spaced apart from each other in a first direction on the active pattern, each of the pair of channel patterns including vertically stacked semiconductor patterns, a source/drain pattern between the pair of channel patterns, a pair of gate electrodes on the channel patterns, an active contact between the pair of gate electrodes, and outer spacers on side surfaces of the pair of gate electrodes. A distance between the outer spacers spaced apart from each other with the active contact therebetween is smaller than a width of the source/drain pattern in the first direction at a first level at which an upper surface of an uppermost semiconductor pattern among the semiconductor patterns is positioned.

公开(公告)号：US20240162309A1

公开(公告)日：2024-05-16

申请号：US18135530

申请日：2023-04-17

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Myung YANG ,  Myunghoon JUNG ,  Seungmin SONG ,  Seungchan YUN ,  Sejung PARK ,  Kang-ill SEO

IPC: H01L29/417 ,  H01L21/822 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/06 ,  H01L29/423 ,  H01L29/66 ,  H01L29/775

CPC classification number: H01L29/41733 ,  H01L21/8221 ,  H01L21/823871 ,  H01L27/0922 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/775

Abstract: Provided is a three-dimensional field-effect transistor (3DSFET) device including: a 1st source/drain region on a substrate, and a 2nd source/drain region on the 1st source/drain region; and a 1st source/drain contact structure on the 1st source/drain region, and a 2nd source/drain contact structure on the 2nd source/drain region, wherein the 2nd source/drain region is isolated from the 1st source/drain region through an interlayer structure, and wherein a spacer is formed at an upper portion of a sidewall of the 2nd source/drain contact structure, between the 1st source/drain contact structure and the 2nd source/drain contact structure.

公开(公告)号：US20230223476A1

公开(公告)日：2023-07-13

申请号：US18124339

申请日：2023-03-21

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Junggil YANG ,  Seungmin SONG ,  Geumjong BAE ,  Dong Il BAE

IPC: H01L29/78 ,  H01L29/423 ,  H01L29/786 ,  H01L29/66 ,  H01L29/417

CPC classification number: H01L29/785 ,  H01L29/42356 ,  H01L29/78696 ,  H01L29/78654 ,  H01L29/78618 ,  H01L29/66772 ,  H01L29/66545 ,  H01L29/42392 ,  H01L29/41775 ,  H01L29/7845 ,  H01L29/66795 ,  H01L2029/7858 ,  H01L29/7848

Abstract: A semiconductor device includes a channel pattern including a first semiconductor pattern and a second semiconductor pattern, which are sequentially stacked on a substrate, and a gate electrode that extends in a first direction and crosses the channel pattern. The gate electrode includes a first portion interposed between the substrate and the first semiconductor pattern and a second portion interposed between the first and second semiconductor patterns. A maximum width in a second direction of the first portion is greater than a maximum width in the second direction of the second portion, and a maximum length in the second direction of the second semiconductor pattern is less than a maximum length in the second direction of the first semiconductor pattern.

公开(公告)号：US20230163214A1

公开(公告)日：2023-05-25

申请号：US18093877

申请日：2023-01-06

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Seungmin SONG ,  Bongseok SUH ,  Junggil YANG ,  Soojin JEONG

IPC: H01L29/78 ,  H01L29/06 ,  H01L29/08 ,  H01L29/423

CPC classification number: H01L29/7853 ,  H01L29/0673 ,  H01L29/0847 ,  H01L29/0653 ,  H01L29/42392

Abstract: An integrated circuit includes a fin active region protruding from a substrate, a plurality of semiconductor patterns on an upper surface of the fin active region, a gate electrode that surrounds the plurality of semiconductor patterns and includes a main gate part on an uppermost one of the plurality of semiconductor patterns and sub gate parts between the plurality of semiconductor patterns, a spacer structure on a sidewall of the main gate part, and a source/drain region at a side of the gate electrode. The source/drain region is connected to the plurality of semiconductor patterns and contacts a bottom surface of the spacer structure. A top portion of the uppermost semiconductor pattern has a first width. A bottom portion of the uppermost semiconductor pattern has a second width smaller than the first width.

公开(公告)号：US20220367513A1

公开(公告)日：2022-11-17

申请号：US17878304

申请日：2022-08-01

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Seungmin SONG ,  Beyounghyun KOH ,  Yongjin KWON ,  Kangmin KIM ,  Jaehoon SHIN ,  JoongShik SHIN ,  Sungsoo AHN ,  Seunghwan LEE

IPC: H01L27/11582 ,  H01L27/11565 ,  H01L27/11573 ,  H01L27/1157

Abstract: A memory device includes a substrate; a stacked structure including a plurality of gate layers and a plurality of interlayer insulating layers that are alternately stacked on the substrate in a vertical direction, the stacked structure including a row of cutouts, each of the cutouts extending in a first horizontal direction and being configured to cut the plurality of gate layers, the cutouts being apart from each other and arranged in a cell region of the stacked structure in the first horizontal direction; and a row of channel structures, the channel structures being arranged in the cell region in the first horizontal direction, each of the channel structures extending in the vertical direction to penetrate the plurality of gate layers.

公开(公告)号：US20220093630A1

公开(公告)日：2022-03-24

申请号：US17241232

申请日：2021-04-27

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Beyounghyun KOH ,  Seungmin SONG ,  Joongshik SHIN ,  Yongjin KWON ,  Jinhyuk KIM ,  Hongik SON

IPC: H01L27/11575 ,  H01L23/535 ,  H01L23/00 ,  H01L27/11548 ,  H01L27/11556 ,  H01L27/11529 ,  H01L27/11582 ,  H01L27/11573 ,  H01L21/768

Abstract: A semiconductor device includes a substrate having cell array and extension regions, a gate electrode structure having gate electrodes stacked in a first direction, a channel through the gate electrode structure on the cell array region, a first division pattern extending in the second direction on the cell array and extension regions, the first division pattern being at opposite sides of the gate electrode structure in a third direction, an insulation pattern structure partially through the gate electrode structure on the extension region, a through via through the insulation pattern structure, and a support layer on the gate electrode structure and extending on the cell array and extension regions, the support layer contacting an upper sidewall of the first division pattern, and the support layer not contacting an upper surface of a portion of the first division pattern on the extension region adjacent to the insulation pattern structure.

公开(公告)号：US20210320125A1

公开(公告)日：2021-10-14

申请号：US17162408

申请日：2021-01-29

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jaehoon SHIN ,  Kangmin KIM ,  Kyeongjin PARK ,  Seungmin SONG ,  Joongshik SHIN ,  Geunwon LIM

IPC: H01L27/11582 ,  H01L27/11573 ,  H01L27/11565 ,  H01L27/11519 ,  H01L27/11526 ,  H01L27/11556 ,  H01L23/522

Abstract: A vertical memory device includes a gate electrode structure, a channel, an insulation pattern structure, an etch stop structure, and a through via. The gate electrode structure includes gate electrodes spaced apart from each other on a substrate in a first direction perpendicular to an upper surface of the substrate, and each of the gate electrodes extends in a second direction parallel to the upper surface of the substrate. The channel extends in the first direction through the gate electrode structure. The insulation pattern structure extends through the gate electrode structure. The etch stop structure extends through the gate electrode structure and surround at least a portion of a sidewall of the insulation pattern structure, and the etch stop structure includes a filling pattern and an etch stop pattern on a sidewall of the filling pattern. The through via extends in the first direction through the insulation pattern structure.

公开(公告)号：US20210111188A1

公开(公告)日：2021-04-15

申请号：US16895364

申请日：2020-06-08

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Seungmin SONG ,  Beyounghyun KOH ,  Yongjin KWON ,  Kangmin KIM ,  Jaehoon SHIN ,  JoongShik SHIN ,  Sungsoo AHN ,  Seunghwan LEE

IPC: H01L27/11582 ,  H01L27/1157 ,  H01L27/11573 ,  H01L27/11565

Abstract: A memory device includes a substrate; a stacked structure including a plurality of gate layers and a plurality of interlayer insulating layers that are alternately stacked on the substrate in a vertical direction, the stacked structure including a row of cutouts, each of the cutouts extending in a first horizontal direction and being configured to cut the plurality of gate layers, the cutouts being apart from each other and arranged in a cell region of the stacked structure in the first horizontal direction; and a row of channel structures, the channel structures being arranged in the cell region in the first horizontal direction, each of the channel structures extending in the vertical direction to penetrate the plurality of gate layers.