公开(公告)号：US20240330171A1

公开(公告)日：2024-10-03

申请号：US18515565

申请日：2023-11-21

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jaeyoung Heo ,  Byeongho Kim ,  Yuhwan Ro ,  Sungjoo Yoo ,  Suk Han Lee

IPC: G06F12/02

CPC classification number: G06F12/023

Abstract: Disclosed is a memory device which includes a plurality of memory chips. Each of the plurality of memory chips includes a plurality of memory banks and a logic circuit. In a first operation mode, the logic circuit writes first data in the plurality of memory banks based on a first command and a first address received from the host, and performs a first processing-in-memory (PIM) operation based on third data received from the host and the first data. In a second operation mode, the logic circuit writes second data in the plurality of memory banks based on the first command and the first address received from the host, and performs a second PIM operation based on fourth data different from the third data received from the host and the second data.