公开(公告)号：US10990589B2

公开(公告)日：2021-04-27

申请号：US15672800

申请日：2017-08-09

Applicant: Samsung Electronics Co., Ltd.

Inventor： Junwhan Ahn ,  Sungjoo Yoo ,  Kiyoung Choi

IPC: G06F16/242 ,  G06F12/0886 ,  G06F12/0846 ,  G06F16/2455 ,  G06F16/245 ,  G06F12/06

Abstract: A computing apparatus may process an operation. The computing apparatus may output information regarding an aggregation operation and an operand corresponding to a variable stored in a memory, store information regarding an operator and the aggregation operands regarding the aggregation operation, perform a first partial operation with respect to the aggregation operands and store a result value of the first partial operation, and process the aggregation operation based on storing the variable, performing a second partial operation with respect to the result value of the first partial operation stored in the cache and the operand corresponding to the variable, and storing a result value of the second partial operation.

公开(公告)号：US20240330171A1

公开(公告)日：2024-10-03

申请号：US18515565

申请日：2023-11-21

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jaeyoung Heo ,  Byeongho Kim ,  Yuhwan Ro ,  Sungjoo Yoo ,  Suk Han Lee

IPC: G06F12/02

CPC classification number: G06F12/023

Abstract: Disclosed is a memory device which includes a plurality of memory chips. Each of the plurality of memory chips includes a plurality of memory banks and a logic circuit. In a first operation mode, the logic circuit writes first data in the plurality of memory banks based on a first command and a first address received from the host, and performs a first processing-in-memory (PIM) operation based on third data received from the host and the first data. In a second operation mode, the logic circuit writes second data in the plurality of memory banks based on the first command and the first address received from the host, and performs a second PIM operation based on fourth data different from the third data received from the host and the second data.

公开(公告)号：US11250320B2

公开(公告)日：2022-02-15

申请号：US15880690

申请日：2018-01-26

Applicant: Samsung Electronics Co., Ltd. ,  Seoul National University R&DB Foundation

Inventor： Junhaeng Lee ,  Sungjoo Yoo ,  Eunhyeok Park

IPC: G06N3/08 ,  G06N3/04 ,  G06N3/063

Abstract: Provided are a neural network method and an apparatus, the method including obtaining a set of floating point data processed in a layer included in a neural network, determining a weighted entropy based on data values included in the set of floating point data, adjusting quantization levels assigned to the data values based on the weighted entropy, and quantizing the data values included in the set of floating point data in accordance with the adjusted quantization levels.

公开(公告)号：US20220108178A1

公开(公告)日：2022-04-07

申请号：US17551572

申请日：2021-12-15

Applicant: Samsung Electronics Co., Ltd. ,  Seoul National University R&DB Foundation

Inventor： Junhaeng Lee ,  Sungjoo Yoo ,  Eunhyeok Park

IPC: G06N3/08 ,  G06N3/04

Abstract: Provided are a neural network method and an apparatus, the method including obtaining a set of floating point data processed in a layer included in a neural network, determining a weighted entropy based on data values included in the set of floating point data, adjusting quantization levels assigned to the data values based on the weighted entropy, and quantizing the data values included in the set of floating point data in accordance with the adjusted quantization levels.

公开(公告)号：US20180253636A1

公开(公告)日：2018-09-06

申请号：US15870767

申请日：2018-01-12

Applicant: Samsung Electronics Co., Ltd. ,  Seoul National University R&DB Foundation

Inventor： Sehwan Lee ,  Dongyoung Kim ,  Sungjoo Yoo

IPC: G06N3/02

CPC classification number: G06N3/02 ,  G06N3/0454 ,  G06N3/063

Abstract: A neural network processor and method include a fetch controller configured to receive input feature information, indicating whether each of a plurality of input features of an input feature map includes a non-zero value, and weight information, indicating whether each of a plurality of weights of a weight map includes a non-zero value, and configured to determine input features and weights to be convoluted, from among the plurality of input features and the plurality of weights, based on the input feature information and the weight information. The neural network processor and method also include a data arithmetic circuit configured to convolute the determined weights and input features to generate an output feature map.