公开(公告)号：US20240330171A1

公开(公告)日：2024-10-03

申请号：US18515565

申请日：2023-11-21

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jaeyoung Heo ,  Byeongho Kim ,  Yuhwan Ro ,  Sungjoo Yoo ,  Suk Han Lee

IPC: G06F12/02

CPC classification number: G06F12/023

Abstract: Disclosed is a memory device which includes a plurality of memory chips. Each of the plurality of memory chips includes a plurality of memory banks and a logic circuit. In a first operation mode, the logic circuit writes first data in the plurality of memory banks based on a first command and a first address received from the host, and performs a first processing-in-memory (PIM) operation based on third data received from the host and the first data. In a second operation mode, the logic circuit writes second data in the plurality of memory banks based on the first command and the first address received from the host, and performs a second PIM operation based on fourth data different from the third data received from the host and the second data.

公开(公告)号：US20240256452A1

公开(公告)日：2024-08-01

申请号：US18339488

申请日：2023-06-22

Applicant: Samsung Electronics Co., Ltd.

Inventor： Shinhaeng Kang ,  Suk Han Lee ,  Kyomin Sohn

IPC: G06F12/0811 ,  G06F12/0891

CPC classification number: G06F12/0811 ,  G06F12/0891

Abstract: Disclosed is a semiconductor memory device and a memory system, including at least one high-bandwidth memory device configured to store data or output stored data according to an access command, a processor configured to generate the access command for the high-bandwidth memory device, and a logic die on the high-bandwidth memory device and including a last level cache providing a cache function to the processor. The last level cache is configured to perform a cache bypassing operation to directly access the high-bandwidth memory device without a cache replacement operation when an invalid line and a clean line do not exist in a cache miss state in response to a cache read or cache write request by the processor.

公开(公告)号：US20240161850A1

公开(公告)日：2024-05-16

申请号：US18362130

申请日：2023-07-31

Applicant: Samsung Electronics Co., Ltd.

Inventor： Byeongho Kim ,  Shinhaeng Kang ,  Suk Han Lee ,  Hweesoo Kim ,  Kyomin Sohn

IPC: G11C29/18 ,  G11C29/12

CPC classification number: G11C29/18 ,  G11C29/1201 ,  G11C2029/1202 ,  G11C2029/1204

Abstract: A memory device which includes a plurality of memory chips. Each of the plurality of memory chips includes a plurality of memory banks and a logic circuit performing a read operation on data stored in the plurality of memory banks based on a first command and a first address received from a host. When a PIM instruction set is stored before the first command and the first address are received, the logic circuit is configured to perform a PIM command execution operation. When an error associated with the PIM command execution operation occurs, the logic circuit is configured to generate error data and record the error data at the log register through the first channels. The logic circuit is configured to output event data indicating an existence of the error data to the host in a first operation mode. The logic circuit is configured to output the error data to the host in a second operation mode.