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    MEMORY DEVICE FOR PERFORMING IN-MEMORY PROCESSING
    2.
    发明申请
    MEMORY DEVICE FOR PERFORMING IN-MEMORY PROCESSING 有权

    公开(公告)号：US20230013611A1

    公开(公告)日：2023-01-19

    申请号：US17954532

    申请日：2022-09-28

    申请人： Samsung Electronics Co., Ltd.

    发明人： Yuhwan Ro ,  Shinhaeng Kang ,  Seongwook Park ,  Seungwoo Seo

    IPC分类号： G06F3/06 ,  G06F7/523 ,  G06N3/063

    摘要： A memory device includes: memory operation circuitries to perform memory processing; memory banks assigned to one of the memory operation circuitries such that a set of n memory banks is assigned to each of the memory operation circuitries; and command pads to receive a command signal from an external source, wherein, for each of the memory operation circuitries, a corresponding memory operation circuitry to access memory banks of a corresponding set of n memory banks that is assigned to the corresponding memory operation circuitry, in an order determined based on respective distances from each of the memory banks of the corresponding set of n memory banks to the command pads, and wherein, each of the memory banks of the corresponding set of n memory banks to perform an access operation of data requested by the corresponding memory operation circuitry while the memory processing is performed.

    MEMORY DEVICE FOR PERFORMING IN-MEMORY PROCESSING
    4.
    发明申请
    MEMORY DEVICE FOR PERFORMING IN-MEMORY PROCESSING 有权

    公开(公告)号：US20210397376A1

    公开(公告)日：2021-12-23

    申请号：US17098959

    申请日：2020-11-16

    申请人： Samsung Electronics Co., Ltd.

    发明人： Yuhwan Ro ,  Shinhaeng Kang ,  Seongwook Park ,  Seungwoo Seo

    IPC分类号： G06F3/06 ,  G06N3/063 ,  G06F7/523

    摘要： A memory device includes: in-memory operation units to perform in-memory processing of an operation pipelined in multi-pipeline stages; memory banks assigned to the plurality of in-memory operation units such that a set of n memory banks is assigned to each of the in-memory operation units, each memory bank performing an access operation of data requested by each of the plurality of in-memory operation units while the pipelined operation is performed, wherein n is a natural number; and a memory die in which the in-memory operation units, the memory banks, and command pads configured to receive a command signal from an external source are arranged. Each set of the n memory banks includes a first memory bank having a first data transmission distance to the command pads and a second memory bank having a second data transmission distance to the command pads that is larger than the first data transmission distance.

    Memory device with internal processing interface
    5.
    发明授权
    Memory device with internal processing interface 有权

    公开(公告)号：US12099455B2

    公开(公告)日：2024-09-24

    申请号：US17591928

    申请日：2022-02-03

    申请人： SAMSUNG ELECTRONICS CO., LTD.

    发明人： Hak-soo Yu ,  Shinhaeng Kang ,  Yuhwan Ro

    IPC分类号： G06F13/16 ,  G06F9/30 ,  G06F13/38 ,  G06F13/40 ,  G06F15/78 ,  G11C7/18 ,  G11C8/14

    CPC分类号： G06F13/1668 ,  G06F9/3016

    摘要： A memory device includes a processor in memory (PIM) circuit including an internal processor configured to perform an internal processing operation, and an interface circuit connected to the PIM circuit, wherein the interface circuit includes a command address decoder configured to decode a command and an address received through first pins to generate an internal command, a second pin configured to receive a voltage signal relating to a control of a PIM operation mode, and a command mode decoder configured to generate at least one command mode bit (CMB) based on the internal command and the voltage signal, and the interface circuit outputs internal control signals to the PIM circuit based on the at least one CMB to control the internal processing operation of the PIM circuit.

    MEMORY DEVICE FOR PROCESSING IN MEMORY AND OPERATING METHOD OF MEMORY DEVICE
    8.
    发明公开
    MEMORY DEVICE FOR PROCESSING IN MEMORY AND OPERATING METHOD OF MEMORY DEVICE 审中-公开

    公开(公告)号：US20240330171A1

    公开(公告)日：2024-10-03

    申请号：US18515565

    申请日：2023-11-21

    申请人： Samsung Electronics Co., Ltd.

    发明人： Jaeyoung Heo ,  Byeongho Kim ,  Yuhwan Ro ,  Sungjoo Yoo ,  Suk Han Lee

    IPC分类号： G06F12/02

    CPC分类号： G06F12/023

    摘要： Disclosed is a memory device which includes a plurality of memory chips. Each of the plurality of memory chips includes a plurality of memory banks and a logic circuit. In a first operation mode, the logic circuit writes first data in the plurality of memory banks based on a first command and a first address received from the host, and performs a first processing-in-memory (PIM) operation based on third data received from the host and the first data. In a second operation mode, the logic circuit writes second data in the plurality of memory banks based on the first command and the first address received from the host, and performs a second PIM operation based on fourth data different from the third data received from the host and the second data.

    Memory device for performing in-memory processing
    10.
    发明授权
    Memory device for performing in-memory processing 有权

    公开(公告)号：US11494121B2

    公开(公告)日：2022-11-08

    申请号：US17098959

    申请日：2020-11-16

    申请人： Samsung Electronics Co., Ltd.

    发明人： Yuhwan Ro ,  Shinhaeng Kang ,  Seongwook Park ,  Seungwoo Seo

    IPC分类号： G06F3/06 ,  G06N3/063 ,  G06F7/523

    摘要： A memory device includes: in-memory operation units to perform in-memory processing of an operation pipelined in multi-pipeline stages; memory banks assigned to the plurality of in-memory operation units such that a set of n memory banks is assigned to each of the in-memory operation units, each memory bank performing an access operation of data requested by each of the plurality of in-memory operation units while the pipelined operation is performed, wherein n is a natural number; and a memory die in which the in-memory operation units, the memory banks, and command pads configured to receive a command signal from an external source are arranged. Each set of the n memory banks includes a first memory bank having a first data transmission distance to the command pads and a second memory bank having a second data transmission distance to the command pads that is larger than the first data transmission distance.