公开(公告)号：US11069706B2

公开(公告)日：2021-07-20

申请号：US16573695

申请日：2019-09-17

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Kang-Won Lee ,  Jaeyoung Song ,  Dong-Sik Lee ,  Donghoon Jang

IPC: H01L27/11582 ,  H01L27/1157 ,  H01L27/115 ,  H01L23/522 ,  H01L23/528 ,  H01L27/06 ,  H01L29/66 ,  H01L29/792 ,  H01L27/11575 ,  H01L27/11556

Abstract: In a 3D semiconductor memory device, a stack structure includes electrodes and first insulating layers disposed between the electrodes. The stack structure has a stair structure on a connection region. A vertical channel structure penetrates the stack structure on a cell array region. A vertical dummy structure penates the stair structure on the connection region. A second insulating layer is selectively disposed on the cell array region. A maximum thickness of the second insulating layer ranges from 1.5 times to 10 times a maximum thickness of the first insulating layer on the second insulating layer. The vertical channel structure includes an abrupt diameter change at a level of a top surface of the second insulating layer. The abrupt diameter change has a surface which is parallel to the top surface of the second insulating layer and is substantially coplanar with the top surface of the second insulating layer.

公开(公告)号：US09757651B2

公开(公告)日：2017-09-12

申请号：US14476020

申请日：2014-09-03

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jaeyoung Song ,  Jinho Jang ,  Ilgeun Bok ,  Sungjun Kim ,  Hyukgoo Lee ,  Wooseong Choi

IPC: G06F3/023 ,  A63F13/48 ,  G08C17/02 ,  G06F3/14 ,  A63F13/42 ,  A63F13/235 ,  A63F13/352

CPC classification number: A63F13/48 ,  A63F13/235 ,  A63F13/352 ,  A63F13/42 ,  A63F2300/552 ,  G06F3/1423 ,  G08C17/02 ,  G09G2330/021 ,  G09G2370/10 ,  G09G2370/12 ,  G09G2370/16 ,  G09G2380/02

Abstract: A method of processing a user input by an electronic device is provided. The method includes receiving a signal from an auxiliary electronic device, providing application information related to the auxiliary electronic device based on the signal, and identifying a program configured to receive a control signal transmitted from the auxiliary electronic device based on the application information.

公开(公告)号：US11587947B2

公开(公告)日：2023-02-21

申请号：US17355824

申请日：2021-06-23

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Kang-Won Lee ,  Jaeyoung Song ,  Dong-Sik Lee ,  Donghoon Jang

IPC: H01L27/11582 ,  H01L27/115 ,  H01L27/1157 ,  H01L27/1156 ,  H01L23/522 ,  H01L27/1158 ,  H01L23/528

Abstract: In a 3D semiconductor memory device, a stack structure includes electrodes and first insulating layers disposed between the electrodes. The stack structure has a stair structure on a connection region. A vertical channel structure penetrates the stack structure on a cell array region. A vertical dummy structure penates the stair structure on the connection region. A second insulating layer is selectively disposed on the cell array region. A maximum thickness of the second insulating layer ranges from 1.5 times to 10 times a maximum thickness of the first insulating layer on the second insulating layer. The vertical channel structure includes an abrupt diameter change at a level of a top surface of the second insulating layer. The abrupt diameter change has a surface which is parallel to the top surface of the second insulating layer and is substantially coplanar with the top surface of the second insulating layer.

公开(公告)号：US20210320126A1

公开(公告)日：2021-10-14

申请号：US17355824

申请日：2021-06-23

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Kang-Won Lee ,  Jaeyoung Song ,  Dong-Sik Lee ,  Donghoon Jang

IPC: H01L27/11582 ,  H01L23/522 ,  H01L27/1157

Abstract: In a 3D semiconductor memory device, a stack structure includes electrodes and first insulating layers disposed between the electrodes. The stack structure has a stair structure on a connection region. A vertical channel structure penetrates the stack structure on a cell array region. A vertical dummy structure penetrates the stair structure on the connection region. A second insulating layer is selectively disposed on the cell array region. A maximum thickness of the second insulating layer ranges from 1.5 times to 10 times a maximum thickness of the first insulating layer on the second insulating layer. The vertical channel structure includes an abrupt diameter change at a level of a top surface of the second insulating layer. The abrupt diameter change has a surface which is parallel to the top surface of the second insulating layer and is substantially coplanar with the top surface of the second insulating layer.