公开(公告)号：US11113063B2

公开(公告)日：2021-09-07

申请号：US16565476

申请日：2019-09-09

Applicant: Samsung Electronics Co., Ltd.

Inventor： James David Dundas ,  Xiaoxin Fan ,  Shashank Nemawarkar ,  Madhu Saravana Sibi Govindan

IPC: G06F9/32 ,  G06F9/34 ,  G06F9/38 ,  H04L9/06 ,  G06F12/1027 ,  G06F9/44 ,  G06F9/46

Abstract: According to one general aspect, an apparatus may include a main-branch target buffer (BTB). The apparatus may include a micro-BTB separate from and smaller than the main-BTB, and configured to produce prediction information associated with a branching instruction. The apparatus may include a micro-BTB confidence counter configured to measure a correctness of the prediction information produced by the micro-BTB. The apparatus may further include a micro-BTB misprediction rate counter configured to measure a rate of mispredictions produced by the micro-BTB. The apparatus may also include a micro-BTB enablement circuit configured to enable a usage of the micro-BTB's prediction information, based, at least in part, upon the values of the micro-BTB confidence counter and the micro-BTB misprediction rate counter.

公开(公告)号：US11169810B2

公开(公告)日：2021-11-09

申请号：US16374743

申请日：2019-04-03

Applicant: Samsung Electronics Co., Ltd.

Inventor： Ryan J. Hensley ,  Fuzhou Zou ,  Monika Tkaczyk ,  Eric C. Quinnell ,  James David Dundas ,  Madhu Saravana Sibi Govindan

IPC: G06F9/30 ,  G06F9/38

Abstract: According to one general aspect, an apparatus may include an instruction fetch unit circuit configured to retrieve instructions from a memory. The apparatus may include an instruction decode unit configured to convert instructions into one or more micro-operations that are provided to an execution unit circuit. The apparatus may also include a micro-operation cache configured to store micro-operations. The apparatus may further include a branch prediction circuit configured to: determine when a kernel of instructions is repeating, store at least a portion of the kernel within the micro-operation cache, and provide the stored portion of the kernel to the execution unit circuit without the further aid of the instruction decode unit circuit.