公开(公告)号：US08951881B2

公开(公告)日：2015-02-10

申请号：US14279786

申请日：2014-05-16

Applicant: Samsung Electronics Co., Ltd.

Inventor： Dong-Sik Lee ,  Jang-Hyun You ,  Jee-Hoon Han ,  Young-Woo Park ,  Sung-Hoi Hur ,  Sang-Ick Joo

IPC: H01L21/76 ,  H01L21/762 ,  H01L21/764

CPC classification number: H01L21/76224 ,  H01L21/76229 ,  H01L21/764

Abstract: A method of fabricating a nonvolatile memory device includes forming trenches in a substrate defining device isolation regions therein and active regions therebetween. The trenches and the active regions therebetween extend into first and second device regions of the substrate. A sacrificial layer is formed in the trenches between the active regions in the first device region, and an insulating layer is formed to substantially fill the trenches between the active regions in the second device region. At least a portion of the sacrificial layer in the trenches in the first device region is selectively removed to define gap regions extending along the trenches between the active regions in the first device region, while substantially maintaining the insulating layer in the trenches between the active regions in the second device region. Related methods and devices are also discussed.

Abstract translation: 制造非易失性存储器件的方法包括在衬底中形成限定器件隔离区域的衬底中的沟槽，并且其间的有源区域。 沟槽和其间的有源区延伸到衬底的第一和第二器件区域。 牺牲层形成在第一器件区域中的有源区之间的沟槽中，并且形成绝缘层以基本上填充第二器件区域中的有源区之间的沟槽。 选择性地去除第一器件区域中的沟槽中的牺牲层的至少一部分，以限定沿着第一器件区域中的有源区之间的沟槽延伸的间隙区域，同时基本上将沟槽中的绝缘层保持在有源区 在第二设备区域中。 还讨论了相关的方法和设备。

公开(公告)号：US11031411B2

公开(公告)日：2021-06-08

申请号：US16505266

申请日：2019-07-08

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Young-Hwan Son ,  Jae-Hoon Jang ,  Jee-Hoon Han

IPC: H01L27/1157 ,  H01L27/11556 ,  H01L27/11519 ,  H01L27/11565 ,  H01L27/11524 ,  H01L27/11529 ,  H01L27/11573 ,  H01L27/11582

Abstract: A vertical non-volatile memory device includes a lower insulating layer on a substrate, a multilayer structure including gate electrodes and interlayer insulating layers alternately stacked on the lower insulating layer, a gate dielectric layer and a channel structure, and has an opening extending through the multilayer structure and exposing the lower insulating layer. The opening includes a first open portion extending through at least one layer of the multilayer structure at a first width, and a second open portion extending through the multilayer structure at a second width less than the first width. The gate dielectric layer lines the opening, and the channel structure is disposed on the gate dielectric layer and is electrically connected to the substrate.

公开(公告)号：US10978464B2

公开(公告)日：2021-04-13

申请号：US15931869

申请日：2020-05-14

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Young-Hwan Son ,  Jae-Hoon Jang ,  Jee-Hoon Han

IPC: H01L27/11556 ,  H01L27/1157 ,  H01L27/11519 ,  H01L27/11565 ,  H01L27/11524 ,  H01L27/11529 ,  H01L27/11573 ,  H01L27/11582

Abstract: A vertical non-volatile memory device includes a lower insulating layer on a substrate, a multilayer structure including gate electrodes and interlayer insulating layers alternately stacked on the lower insulating layer, a gate dielectric layer and a channel structure, and has an opening extending through the multilayer structure and exposing the lower insulating layer. The opening includes a first open portion extending through at least one layer of the multilayer structure at a first width, and a second open portion extending through the multilayer structure at a second width less than the first width. The gate dielectric layer lines the opening, and the channel structure is disposed on the gate dielectric layer and is electrically connected to the substrate.

公开(公告)号：US20200273870A1

公开(公告)日：2020-08-27

申请号：US15931869

申请日：2020-05-14

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Young-Hwan Son ,  Jae-Hoon Jang ,  Jee-Hoon Han

IPC: H01L27/11556 ,  H01L27/11519 ,  H01L27/11565 ,  H01L27/11524 ,  H01L27/1157 ,  H01L27/11529 ,  H01L27/11573 ,  H01L27/11582

Abstract: A vertical non-volatile memory device includes a lower insulating layer on a substrate, a multilayer structure including gate electrodes and interlayer insulating layers alternately stacked on the lower insulating layer, a gate dielectric layer and a channel structure, and has an opening extending through the multilayer structure and exposing the lower insulating layer. The opening includes a first open portion extending through at least one layer of the multilayer structure at a first width, and a second open portion extending through the multilayer structure at a second width less than the first width. The gate dielectric layer lines the opening, and the channel structure is disposed on the gate dielectric layer and is electrically connected to the substrate.

公开(公告)号：US08878332B2

公开(公告)日：2014-11-04

申请号：US14248517

申请日：2014-04-09

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jong-Hoon Na ,  Young-Woo Park ,  Dong-Hwa Kwak ,  Tae-Yong Kim ,  Jee-Hoon Han ,  Jang-Hyun You ,  Dong-Sik Lee ,  Su-Jin Park

IPC: H01L21/70 ,  H01L21/76 ,  H01L27/02 ,  H01L27/11

CPC classification number: H01L27/0207 ,  H01L21/28273 ,  H01L27/11 ,  H01L27/11519 ,  H01L27/11524

Abstract: A method of fabricating a nonvolatile memory device includes providing a substrate having active regions defined by a plurality of trenches, forming a first isolation layer on the substrate having the plurality of trenches, forming a sacrificial layer on the first isolation layer to fill the trenches, the sacrificial layer including a first region filling lower portions of the trenches and a second region filling portions other than the lower portions, removing the second region of the sacrificial layer, forming a second isolation layer on the first isolation layer and the first region of the sacrificial layer, forming air gaps in the trenches by removing the first region of the sacrificial layer, and removing a portion of the first isolation layer and a portion of the second isolation layer while maintaining the air gaps.

Abstract translation: 一种制造非易失性存储器件的方法包括提供具有由多个沟槽限定的有源区的衬底，在具有多个沟槽的衬底上形成第一隔离层，在第一隔离层上形成牺牲层以填充沟槽， 所述牺牲层包括填充所述沟槽的下部的第一区域和除所述下部以外的第二区域填充部分，去除所述牺牲层的所述第二区域，在所述第一隔离层上形成第二隔离层和在所述第一隔离层的所述第一区域 牺牲层，通过去除牺牲层的第一区域在沟槽中形成气隙，以及在保持气隙的同时去除第一隔离层的一部分和第二隔离层的一部分。

公开(公告)号：US20140248755A1

公开(公告)日：2014-09-04

申请号：US14279786

申请日：2014-05-16

Applicant: Samsung Electronics Co., Ltd.

Inventor： Dong-Sik Lee ,  Jang-Hyun You ,  Jee-Hoon Han ,  Young-Woo Park ,  Sung-Hoi Hur ,  Sang-Ick Joo

IPC: H01L21/762

CPC classification number: H01L21/76224 ,  H01L21/76229 ,  H01L21/764

Abstract: A method of fabricating a nonvolatile memory device includes forming trenches in a substrate defining device isolation regions therein and active regions therebetween. The trenches and the active regions therebetween extend into first and second device regions of the substrate. A sacrificial layer is formed in the trenches between the active regions in the first device region, and an insulating layer is formed to substantially fill the trenches between the active regions in the second device region. At least a portion of the sacrificial layer in the trenches in the first device region is selectively removed to define gap regions extending along the trenches between the active regions in the first device region, while substantially maintaining the insulating layer in the trenches between the active regions in the second device region. Related methods and devices are also discussed.

Abstract translation: 制造非易失性存储器件的方法包括在衬底中形成限定器件隔离区域的衬底中的沟槽，并且其间的有源区域。 沟槽和其间的有源区延伸到衬底的第一和第二器件区域。 牺牲层形成在第一器件区域中的有源区之间的沟槽中，并且形成绝缘层以基本上填充第二器件区域中的有源区之间的沟槽。 选择性地去除第一器件区域中的沟槽中的牺牲层的至少一部分以限定沿着第一器件区域中的有源区之间的沟槽延伸的间隙区域，同时基本上将绝缘层保持在有源区域之间的沟槽中 在第二设备区域中。 还讨论了相关的方法和设备。